Glasgow ASIC Event

In Person

With support from Mahmoud Wagih, Professor of Responsible & RF Electronics, we will be holding an in person SoC design workshop at the University of Glasgow. The full day event will be a great way to get involved in SoC development and we hope to bring together potential chip designers from Glasgow and beyond. The workshop will introduce SoC Labs, provide practical training on SoC design using the SoC Labs silicon proven reference designs and finally explore opportunities for collaborative SoC design projects, and help form project teams. We hope teams will take part in the UK System on Chip Design Contest 2026/27, which provides an opportunity for funding towards tape out of an ASIC based SoC design. We look forward to seeing academics, researchers, students and engineers no matter whether they have some IC design experience our would like to gain the skills and experience. 

The UK System-on-Chip Design Accelerator is part of the UK Semiconductor Strategy and AI Hardware Plan with the goal of improving the design and tape-out capability within the UK research and start up community.

The workshop is open to anyone with an interest in electronic systems design even if you have no prior experience in chip design. The workshop will provide a detailed overview of all the steps needed to design and fabricate a CMOS ASIC design. It will then look to create collaborations to develop actual projects that will receive support and an opportunity to fund silicon manufacture. 

You come with;

        A one or two slide presentation / sketch of your design idea if you have one

You will leave the workshop with;

        practical SoC and IC design skills
      collaborators and the opportunity to turn your design concept into physical silicon (or to build your skills on a real project even if you don’t have a concept)

Projects developed at the workshop will be supported by SoC Labs to turn your ideas to silicon, both financially and technically. It is expected that successful design with be fabrication in a range of processes from 65 nm to advanced node 16 nm FinFET.

AGENDA:  

• 9.30: Arrival Coffee, Networking. 
• 10.00: Introduction to SoC Labs and the UK System-on-Chip Design Accelerator
• 10.30: Re-usable SoC reference designs to accelerate your design goals, how to design and as importantly verify a complete SoC design. 
• 12:30: Lunch
• 1:30: The design flow journey from design concept to silicon manufacture and post silicon bring up. 
• 2:30: Participant pitches: attendees pitch their design concepts to potential collaborators.
• 3:15: Group SoC Sandpit form teams for potential SoC design projects. 

Date & Time:

4 December 2026, 9.30-4 pm. To be hosted at the University of Glasgow. 

Please register here