milliSoC project specification and rationale 

nanoSoC runs on the HAPS-SX as the standing bench image (the ethernet-chiplet build), proving the board, the programming path and the debug environment before megaSoC.

A DDR4 variant that reads and writes the board’s 16 GB DDR4 SODIMM through the shared megasoc_dram_wrapper is built, passes an 8 GB memtest in simulation and meets timing; its first run on the board is scheduled. It is the vehicle for proving the DDR path before the same wrapper goes into the megaSoC FPGA build.

Set Up a Project in the SoC Labs Version Control.

The project is using an agile method so the the project structure will evolve. An initial project structure should allow for the initial Minimal Viable Product deliverables:

1.  a knowledge base for the community on the HAPS system including set up requirements and other documentation

2.  a course on using HAPS as part of a real world System on Chip project. 

Board support lives in the HAPS work repository (fpga/haps-sx build targets, standalone calibration designs, firmware, bench runbooks); the megaSoC FPGA target lives with the megaSoC project.

• NanoSoC running on PYNQ-Z2.
• TFLM toolchain setup.
• Custom TF model built and running on FPGA.

The guidance for the Getting Started milestone states it should help determine the best way to manage the project and to provides a simple way to manage the activities to be completed.

Project Management:

This project is not a System on Chip activity that follows the normal path of design flow steps. This project will selectively use some of the design flow steps and add some free form milestones as a way to guide the project to meet target dates to better drive the project to completion. As milestones are completed the date and details of the work need to be captured.

Design Method:

The project will use an agile method, with short development cycles, this will allow user needs to be established and then delivered. Agile usually defines a first iteration as a Minimal Viable Product.  

Access to IP:

There are two aspects to this project: 

1.  defining the IP needed from Synopsys for the HAPS operations
2.  defining an initial SoC design that will act as a reference model for deployment that can be used by the community as an example.

Synopsys IP:

SoC design IP:

Version Control:

Until a better alternative can be identified any materials developed by this project should be held in the SoC Labs git repository. 

Project Structure:

This will need to be defined in more detail as we understand the use cases and information and other assets that need to be developed as part of the project.

The initial known outputs are:

1.  a knowledge base for the community on the HAPS system including set up requirements and other documentation
2.  a course on using HAPS as part of a real world System on Chip project.

Verification Methodology:

As outlined part of the project is to follow a typical SoC Labs reference design flow deployment using the HAPS to allow the three major uses of FPGA prototyping environments:

1.  verifying the synthesizable RTL source code
2.  integration into a Continuous Integration and Deployment service for team based projects
3.  support hardware/software co-design with test software on the prototype SoC design

Both MVP deliverables are defined and the first exists. The community knowledge base is the HAPS-SX Development space on the SoC Labs Confluence (getting started, network and command-line configuration, adding a board, HOSTIO and OpenOCD debug, ConfPro-SX on WSL, DDR memtest runbook). The course has not been started.

A custom SoC for recording and stimulating nerve and muscle signals: it senses an electrode's electrical activity and delivers safe, controlled pulses back through the same electrodes. Built on the nanoSoC reference design with an Arm Cortex-M0.

It combines an analog front-end and dual-mode data converters (fast SAR for spikes, high-resolution ΔΣ for slow baseline drift) with a stimulation path that has hardware-level current limiting. A single hardware trigger edge starts stimulation and acquisition together, giving deterministic stim-to-record timing with no software jitter. Four electrodes are shared between record and stim through a switch.

SYNAPSE's project structure is set up following the SoC Labs accelerator-project template. The design lives in its own repo with rtl/, models/, tb/ and docs/, linked as a submodule (synapse) of a private fork of accelerator-project. projbranch and ACCELERATOR_DIR are updated, and the nanoSoC flow environment runs under WSL2 Ubuntu (Icarus Verilog, GTKWave). Save and update scripts keep the design repo and the fork in sync with upstream. Arm IP (Cortex-M0, DMA) is pending Arm Academic Access.

Simulation environment setup and working