The global academic community for Arm based System on Chip design
Join our communitySign Up

Our goals are simple, to help:

  • You: to develop industrially relevant, real world, silicon proven, SoC design skills that you need in your research and become one of the next generation of chip designers.
  • Each other: learn, solve problems and get to results faster. Industrial SoC design is a team effort. Community centric hardware design helps us all create, verify, and fabricate better custom silicon.
  • Reuse prior knowledge: by using reference designs, tested, validated ‘blueprints’ for Systems, you can quickly integrate your innovative research, simplifying the effort needed to fabricate real silicon devices

Providing state-of-the-art System on Chip design skills needed for the next wave of AI hardware innovation

Training: See our training schedule for workshops and events.

Share experience: Join our projects, add comments, declare interests...

Build your SoC: Select design IP, follow the design flow, create your silicon!


Feel free to use the site's resources, use the navigation icons within the pages and the navigation scheme above

Below you will see the core reusable reference designs the community maintain to simplify and lower the cost of academic SoC design.

Reference Design
Cover image
nanoSoC demo: kNN project
nanoSoC
A simple, low cost, entry level microcontroller SoC extendable for custom accelerators or simple signal processing, ideal for PhD or other students.
Reference Design
Cover image
MilliSoC architecture
milliSoC
A mid-range SoC targeting low latency needs such as RF / radar signal processing, constrained AI models, low resolution real-time video, for small team project.
Reference Design
Cover image
Megasoc architecture
megaSoC
A high end SOC, suitable for larger AI models that require deployment on both CPU and custom accelerator, full resolution video, or other subsystems, ideal for team based research.
Title nanoSoC milliSoC megaSoC
Class Entry Mid Range High End
Processor(s) M0 R5 A53
Processor(s) (speed) <250 Mhz 250-800 MHz 1 GHz
Virtual Prototype Environment Xilinx ZCU104 Arm MPS3 HAPS

Examples of academic tape ours using the Arm ecosystem

Known Good Dies

Take part in one of our design contests and get support for you silicon fabrication tape out

Article
UK System on Chip Design Contest 26-27 Cover image

The  UK System-on-Chip Design Accelerator announced under the  UK AI Hardware Plan has received funding from EPSRC to help support SoC design projects undertaken by individuals and teams in UK university/research institutions. As part of the activity, we are pleased to announce a UK specific design contest for 2026/2027. 

The competition follows the usual SoC Labs methodology of two separate tracks, 

  • an education/collaboration aimed at those with little SoC design skills and no prior tapeout experience,
  • a hardware design track focused on novel designs for those with some previous SoC design experience. 

Take part in one of our design contests and get support for you silicon fabrication tape out

Article
SoC Design Contest 2026 for Canada and the America's Cover image

In association with CMC Microsystems and Arm we are extending our design contest specifically supporting institutions from Canada and the America's with support for their projects, conference attendance and financial help with silicon tape out. 

The contest will again support two alternate tracks: 

  1. Collaboration/Education track focuses on developing SoC design skills  within the academic community and broadening the range of institutions undertaking SoC design activity. The focus is on how teams develop community collaborations and clearly show institutional and individual skill development in SoC design. It does not require a unique hardware concept
  2. Hardware Implementation track focuses on innovative design for a) a mixed signal SoC containing both analogue front end and digital components or b) a SoC that clearly demonstrates how compute (including custom acceleration) makes use of real world data to show clear impact. There is no prescribed analog / digital bias, custom compute / traditional analog is acceptable.