To clarify — the standalone `pynq_sdio_project` was scoped specifically for FPGA validation purposes, containing only the RTL files needed to verify the controller in isolation on the PYNQ-Z2. Now that functional validation is complete, this will be processed for SoC flow along with the MegaSoC project.

Good call on the reference design grounding — I'll add a section that ties the reuse principle to verification methodologies used in our reference designs.

Sorry for the confusion. As described in the Update 01/10/26, the standalone LPDDR4 subsystem is verified against its planned standalone test list (T1–T8). It is now integrated into MegaSoC as a submodule. It is wired in behind a build option (INC_LPDDR4), with an AXI async bridge, an AHB→APB async bridge, and plumbing from the chip down to the testbench. Both builds compile clean, and as of today the A53 firmware brings up the DRAM and the first read/write tests (T1–T3) pass inside MegaSoC.