Verification Methodology

Every project should have a defined Verification Methodology. This can range from highly formal to more agile approaches. The key even if using a less formal methodology is to define clearly how you plan to verify your System on Chip design.

Universal Verification Methodology (UVM) is a standard to create a modular reusable generic verification environment. It aims to reduce the effort of reusing IP by making it easier to reuse verification components associated with the IP.

UVM provides an architectural framework and class libraries for establishing verification environments for a Design Under Test (DUT). A Testbench is a flexible way to create a structured approach to verify IP. It instantiates the IP as a DUT and Test which contains a set of configured verification components and applies sequences of transactions to the DUT. The verification environment for a SoC will contain a hierarchy of Environment components with typically one per IP component. An Agent within the Environment manages a stimulus flow of transaction that are applied to the DUT. Within the Agent transactions from a Sequencer are past to a Driver that converts the transaction-level stimuli into pin-level stimuli and probe the DUT interface with drive signals. A Monitor captures the output of the DUT and converts the pin-level activity to transactions which are passed into the verification environment for analysis. A Scoreboard uses a reference model to check the behavior of DUT comparing the actual and expected transactions flowing through the various Agents.

UVM provides a level of abstraction to the verification process using Transaction Level Modeling (TLM) and also allows for mixed-language verification environments. While the UVM provides an interoperable standard for creating components within a verification environment there are still different implementation choices which need to be considered at this stage of the SoC project.

 The the IEEE 1800.2-2020 standard illustrates how UVM can be implemented in SystemVerilog but as with any architectural design pattern and object model it can be implemented in other description languages. One such option in Python. pyuvm implements a significant portion of the IEEE 1800.2 standard. It fully implements the UVM Transaction Level Modeling (TLM) system. It also uses another Python based framework, cocotb, to interact with simulators and schedule simulation events. It supports both open source tools such as Verilator as well as industry provided EDA tools.