Architectural Design

Architectural design diagram

The concept of reusable design patterns is familiar to many disciplines. At SoC Labs we are interested in reusable design patterns incorporating Arm based components with parts that are unique to your specific research challenge.

Arm itself uses the term Architecture for defining the processor instruction set, programmers' model and memory model, but not implementation details such as cache sizes. Your SoC design is likely a selection and configuration of Arm IP to define the main architecture with specific blocks either developed uniquely or existing third party blocks modified or arranged in a novel way.

The first step is determining the information needed to begin architectural design. Often described as a Specification it should include a list of the proposed uses, specific algorithms or calculations that are to be implemented, time critical operations, etc.

Based on the Specification the next step is to select design components or IP Selection.

At this high level stage of the design process their is less interested in ultimate use of area, power or performance. The interest is in relative observations for different architectural design decisions. The tools available usually rely on static information for area, power and performance that is adjusted/calculated from available configuration database as different architectural designs are evaluated. This can be high level selection such as which processor to use or more fine grained in terms of data paths, cache sizes, etc.   

Explore This Design Flow

Projects Using This Design Flow

Competition 2024
Competition: Collaboration/Education

IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL.
Competition 2024
Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage
Reference Design
Active Project
dwn @ soclabs

nanosoc re-usable MCU platform
Collaborative
Request of Collaboration

DMA Infrastructure Developments

Experts and Interested People

Members

 
Research Area
Low power system design
Role
Consultant

Related Project Milestones

Project Name Target Date Completed Date Description
ARM Cortex M0 Based SoC for Biomedical Applications Architectural Design

In this milestone, we aim to define the hardware used in the SoC. Behavioural level code has been written in Verilog to allow protocol conversion between AHB Lite protocol used in ARM Cortex M0 and UART/I2C peripheral.

Battery Management System-on-chip (BMSoC) for large scale battery energy storage Architectural Design
  1. Understanding the scope of the competitions and going through the reference designs provided in soclabs.org
  2. Top-level block-design for the Mixed-signal applications
  3. Partitioning of Analog and Digital Regions
Low-Cost and Low-Power Data Acquisition System(DAQs) for Real-time Data Collection Architectural Design

Requirements Specification:

The DAQs has two modules - the Gateway and the End-terminal.

End-Terminal Requirements:

Purpose: Outdoor device for gathering real-time environment data

Inputs Power button, 5 sensor connectors:

Outputs: Antenna, 3 indicators - active, low power & power good

Functions: monitors  5 water quality parameters - PH, TDS, Temperature, Turbidity & ???;  transmits

IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL. Architectural Design

structural design of the project

ARM Cortex M0 Based SoC for Biomedical Applications Architectural Design

After defining the customized hardware for the UART and I2C interfaces, we develop customized software. This will help the user and programmers to work with the SoC without worrying about the underlying hardware.

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