Architectural Design

Architectural design diagram

The concept of reusable design patterns is familiar to many disciplines. At SoC Labs we are interested in reusable design patterns incorporating Arm based components with parts that are unique to your specific research challenge.

Arm itself uses the term Architecture for defining the processor instruction set, programmers' model and memory model, but not implementation details such as cache sizes. Your SoC design is likely a selection and configuration of Arm IP to define the main architecture with specific blocks either developed uniquely or existing third party blocks modified or arranged in a novel way.

The first step is determining the information needed to begin architectural design. Often described as a Specification it should include a list of the proposed uses, specific algorithms or calculations that are to be implemented, time critical operations, etc.

Based on the Specification the next step is to select design components or IP Selection.

At this high level stage of the design process their is less interested in ultimate use of area, power or performance. The interest is in relative observations for different architectural design decisions. The tools available usually rely on static information for area, power and performance that is adjusted/calculated from available configuration database as different architectural designs are evaluated. This can be high level selection such as which processor to use or more fine grained in terms of data paths, cache sizes, etc.   

Explore This Design Flow

Projects Using This Design Flow

Competition 2024
Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage
Reference Design
Active Project
d.wf @ soclabs

nanosoc re-usable MCU platform
Collaborative
Request of Collaboration

Lightweight DMA Infrastructure

Experts and Interested People

Members

 
Research Area
VLSI systems resource-constrained applications, Low Power Design Techniques, Machine learning hardware design, Signal Processing Algorithm and VLSI Architectures, Digital Arithmetic, Biomedical Devices. AI/ML, Nanoscience & Technology
Role
Professor
 
Research Area
Design time power estimation using ML
Role
Research staff

Related Project Milestones

Project Name Target Date Completed Date Description
Battery Management System-on-chip (BMSoC) for large scale battery energy storage Architectural Design
  1. Layout Planning
  2. Partitioning of Analog and Digital Regions

Actions

Log-in to Add to Your Profile

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.