The goal of this project is to design and train a CNN model for spoken digit classification and deploy it on a low-cost system-on-chip (SoC) built around an ARM Cortex-M0 microcontroller with a dedicated CNN accelerator. The SoC will be deployed as a prototype on an FPGA. Its throughput, latency and energy consumption per inference, along with its FPGA resource utilisation, will then be evaluated and compared against other systems.

This project focuses on the design and FPGA implementation of a low-power hardware accelerator for a Finite Impulse Response (FIR) filter, intended to reduce noise in speech signals before speech recognition. The accelerator uses a 32-tap, 16-bit serial multiply-accumulate architecture that reuses one signed multiplier and one accumulator to reduce hardware cost and energy consumption. The FIR algorithm is verified using a MATLAB model and RTL simulation.

In this project, we would like to integrate our TsetlinMachine Hardware Accelerator into nanoSOC and tapeout the design.

Precision timekeeping is a foundational service in any distributed system. Whether synchronising Ethernet frames to a PTP grandmaster, timestamping die-to-die packet exchanges between chiplets, or scheduling time-critical hardware events, the system needs a clock that is accurate, capturable at multiple points simultaneously, and adjustable by both hardware servo loops and software without stopping.