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System Verification of NanoSoC 3 weeks ago 1
SHA-2 Accelerator Engine 3 months 4 weeks ago 1
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Authored Comments

Subject Comment Link to Comment
Communication Page Layout

Is it worth splitting with the communication page into three sections; one on on-chip communications, one on Wired off-chip communications and one of Wireless off-chip communications? 

Would it also be worth adding additional communication methods such as USB, SPI, JTAG and UART?

Thank you,

David

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AMBA Guide

Do we want to have a basic guide on this page discussing the different AMBA bus architectures? Explaining the basic difference between APB, AHB and AXI along with the hardware and example hardware required (address decoders, arbiters)?

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Corelink Guide

Would it be worth having a table or breakdown on the differences between the different corelink modules? There is some good information on the arm website https://www.arm.com/products/silicon-ip-system/corelink-interconnect/nic which I think we should try and replicate. 

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Bluetooth Design IP

Is there any Arm/Open-source design IP or example chips which can be used for Bluetooth LE?

I have previously used Nordic NRF Chips but do we want to find example projects that can be used to communicate with Custom SoC's? 

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NFC Modules

As with the bluetooth, do we want to find some example NFC designs or IP that we can put on this page?

I have previously used NFC Chips which are communicated with Arm-based SoC's via SPI and I can go and find out what chips I used. Would this be helpful?

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NFC RFID

Should the NFC page be a subsection of the RFID page as NFC is just a subset of RFID? https://www.atlasrfidstore.com/rfid-insider/rfid-vs-nfc/

 

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Core Breakdown

Is it worth having a table to breakdown the differences/usecases between each cores?

I think specifying which cores are actually being used in current multi-accelerator SoC's would also be a good thing to share so we reduce the type of cores being developed for at one time.

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Accelerator Breakdown

I think Characterising the types of accelerators might be a good idea, such as Graphics accelerators and ML accelerators to make it easier to distinguish which accelerators are used where. 

Along with this, I think we should have a standardised table to specify bus compatibility and throughput specifications/limitations for each accelerator to make it easier for researchers to make an educated decision into which accelerator to use in their project.

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Used Technologies

Along with a brief description for each corestone subsystem on this page, we should also document the IP used in each subsystem and link it back to the relevant page in technology. 

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Peripherals vs Technology

Where do we draw the line before communications and peripherals? UART and SPI are arguably communications also

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