Image of M0 major components
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The Cortex-M0 is a 32 bit processor is targeted at SoCs that require a low gate count (12-25k gates), small die area, high energy efficiency (0.012 mW/MHz Min Power with 50 MHz Max Freq) and is intended for microcontroller and embedded applications.

The processor core implements the ARMv6-M architecture and supports In-order execution. Supports Thumb (16 bit) and subset of Thumb-2 (32/16 bit) instructions for code density / execution performance optimisation. A simple 3-stage pipeline (fetch, decode, execute) is advanced as each instruction is executed.

The bus mechanism (Advanced Microcontroller Bus Architecture AMBA-3) implements the AHB-lite protocol which is a simplified version of Advanced High-performance Bus (AHB) using a single master design. 

The Nested Vector Interrupt Controller (NVIC) supports up to 32 interrupt inputs from peripherals each having  four programmable priority levels which can be used based on the needs of the SoC design. There are additional interrupts for internal process exceptions and a Non-Maskable Interrupt (NMI) input.

Supports sleep states for ultra low-power standby to extend battery life, uses low gate count Wake-Up Interrupt Controller (WIC).

The Debug Access Port (DAP) is an optional component, defined by v5.1 of the ARM Debug interface specification.

Programmed fully in C, no assembler required.

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