Academic Institution


Research Area
Formal modelling
Research Area
Formal System Development
Research Area
Cyber-physical systems
Senior Research Fellow
Research Area
Dean of the Faculty of Engineering and Physical Sciences
Research Area
Advanced Packaging
Cleanroom Process Integration Engineer
Research Area
Security of Hardware
National Teaching Fellow
Research Area
Microwaves, Antennas, RFID/RFIC, Packaging
UK IC Research Fellow and Proleptic Lecturer

Known Good Dies

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

COILS-C1 65nm SoC with M0 cores in 3D stack

Low-cost 3D die stacking using near-field wireless communication.

This two-tier SoC, fabricated using a TSMC 65nm process, incorporates two Arm Cortex M0 CPU cores in addition to a wireless vertical AHB lite bus for inter-layer power and data transfer. The wireless AHB-Lite bus consists…

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

ICL Experimenter 2018

Taped-out in May 2018, ICL-Experimenter is the first in a series of Arm-ECS research centre test-chips designed to explore wireless 3D integration using inductive coupling links. The chip was fabricated in AMS 0.35um technology with two vertically stacked dies within each IC. This initial pr…

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

Pipistrelle-4 65nm low power multi-project SoC

Pipistrelle-4, is the latest in a series SoCs for demonstrating multiple student projects in low-energy systems. Various circuit/system ideas from multiple researcher focusing on energy and performance with optimised SRAM bitcell and low-area overhead energy-efficient flip-flops.


University of Southampton

United Kingdom of Great Britain and Northern Ireland (the)
Members 25
Projects 9
Articles 4
Contributor since: Wed, 06/30/2021 - 14:50
AAA Member



Reference Design
Active Project
DMA 350 integration with nanoSoC

The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC.  This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.

Active Project
System Verification of NanoSoC

Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. With NanoSoC, there are multiple options for performing system-level verification.

Competition: Collaboration/Education
Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference
Project Motivation and Goals

The k-Nearest-Neighbours (kNN) algorithm is a popular Machine Learning technique that can be used for a variety of supervised classification tasks. In contrast to other machine learning algorithms which "encode" the knowledge gained from training data to a set of parameters, such as weights and biases, the parameter set of a kNN classifier consists of just labelled training examples. Classification of an unlabelled example takes place by calculating its Euclidean distance (or any other type of distance metric) from all the stored training examples.

Reference Design
Active Project @ soclabs

nanosoc re-usable MCU platform
A small SoC development framework to support research demonstrator designs