Academic Institution

People

Research Area
Formal modelling
Role
Researcher
Name
Research Area
Formal System Development
Role
Lecturer
Research Area
Cyber-physical systems
Role
Senior Research Fellow
Research Area
UML-B
Role
Dean of the Faculty of Engineering and Physical Sciences
Research Area
Advanced Packaging
Role
Cleanroom Process Integration Engineer
Research Area
Security of Hardware
Role
National Teaching Fellow
Research Area
Microwaves, Antennas, RFID/RFIC, Packaging
Role
UK IC Research Fellow and Proleptic Lecturer

Known Good Dies

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

COILS-C1 65nm SoC with M0 cores in 3D stack

Low-cost 3D die stacking using near-field wireless communication.

This two-tier SoC, fabricated using a TSMC 65nm process, incorporates two Arm Cortex M0 CPU cores in addition to a wireless vertical AHB lite bus for inter-layer power and data transfer. The wireless AHB-Lite bus consists…

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

ICL Experimenter 2018

Taped-out in May 2018, ICL-Experimenter is the first in a series of Arm-ECS research centre test-chips designed to explore wireless 3D integration using inductive coupling links. The chip was fabricated in AMS 0.35um technology with two vertically stacked dies within each IC. This initial pr…

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

Pipistrelle-4 65nm low power multi-project SoC

Pipistrelle-4, is the latest in a series SoCs for demonstrating multiple student projects in low-energy systems. Various circuit/system ideas from multiple researcher focusing on energy and performance with optimised SRAM bitcell and low-area overhead energy-efficient flip-flops.

P…

University of Southampton

Country
United Kingdom of Great Britain and Northern Ireland (the)
Members 28
Projects 15
Articles 4
Contributor since: Wed, 06/30/2021 - 14:50
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Projects

Reference Design
Active Project
Nanosoc ADC Integration
SoClabs

ADC Integration in nanoSoC
Rationale

The aim of this project is to define a mixed signal subsystem for the nanosoc reference design. 

In order to interface with real-world signals in a digital SoC, an analog to digital conversion is needed. The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system. 

Reference Design
Active Project
High bandwidth expansion subsystem block diagram
SoClabs

High Bandwidth Expansion Subsystem
The high bandwidth expansion subsystem is for use in systems where high bandwidth transfer to the hardware accelerator is required. This subsystem can be added to a larger SoC through the 2x full AXI ports (1 subordinate and 1 manager).
Reference Design
Active Project
3D Render of nanoSoC test board

nanoSoC Test/development Board

A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board needs to provide a complete test environment for ASIC designs based on the nanoSoC reference design and enable showcase of any custom designs that utilise it. Reviewing the function of nanoSoC identifies a number of design criteria for the test board:

Serial Wire Debug (SWD) and UART debugger interfaceGPIO driver interface including data transportPower supply and monitoringClock and reset control

Based on these requirements, the following test board is under development:

Collaborative
Request of Collaboration

Interfacing with the Arm PL022 within a cocotb testbench

The Arm PL022 provides an interface for synchronous serial communication with peripheral devices connected to the  SoC via the Advanced Peripheral Bus (APB). It supports a choice of interface operation, Motorola compatible Serial Peripheral Interface (SPI), National Semiconductor Microwire, or Texas Instruments synchronous serial interface. See the Techology page for details.