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Known Good Dies
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Low-cost 3D die stacking using near-field wireless communication.
This two-tier SoC, fabricated using a TSMC 65nm process, incorporates two Arm Cortex M0 CPU cores in addition to a wireless vertical AHB lite bus for inter-layer power and data transfer. The wireless AHB-Lite bus consists…
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Taped-out in May 2018, ICL-Experimenter is the first in a series of Arm-ECS research centre test-chips designed to explore wireless 3D integration using inductive coupling links. The chip was fabricated in AMS 0.35um technology with two vertically stacked dies within each IC. This initial pr…
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The first tape out of the nanoSoC Cortex M0 based SoC Reference Design. This reference design provides a simple microcontroller system appropriate to host and support the development and evaluation of research IP blocks or subsystems. It supports seamless transition from FPGA to physical silicon …
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The aim of this project is to define a mixed signal subsystem for the nanosoc reference design.
In order to interface with real-world signals in a digital SoC, an analog to digital conversion is needed. The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system.
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A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board provides a complete test environment for ASIC designs based on the nanoSoC reference design and enables the showcase of any custom designs that utilise it. Reviewing the function of nanoSoC identifies a number of design criteria for the test board:
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The Arm PL022 provides an interface for synchronous serial communication with peripheral devices connected to the SoC via the Advanced Peripheral Bus (APB). It supports a choice of interface operation, Motorola compatible Serial Peripheral Interface (SPI), National Semiconductor Microwire, or Texas Instruments synchronous serial interface. See the Techology page for details.