Academic Institution
People
Name
Research Area
Learning technologies
Role
Lecturer
Name
Research Area
Machine Learning on Resource-Constrained Embedded Systems
Role
PhD Student
Name
Role
SoC Labs Team
Name
Research Area
IoT Devices
Role
Digital Design Engineer
Name
Role
PhD Researcher
Name
Research Area
Digital Signal Processing
Role
Intern
Name
Role
Student
Name
Research Area
Synthesis
Role
Student
University of Southampton
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Country
United Kingdom of Great Britain and Northern Ireland (the)
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Members |
48 |
Projects |
38 |
Articles |
8 |
Contributor since: |
Wed, 06/30/2021 - 14:50 |
| AAA Member |
Actions
Projects
Collaborative
Active Project
This project demonstrates running the lwIP UDP/IP stack on a MicroBlaze soft processor within an XIlinx PYNQ-Z2 FPGA to create a simple embedded Ethernet communications subsystem. The design integrates a custom Ethernet PHY interface and AXI EthernetLite MAC to enable basic networking functionality. An lwIP echo server runs on the MicroBlaze, while the Zynq Processing System hosts a UART bridge application for host communication. The project is being used to undertake design exploration for soft-core processors in FPGA logic to implement and verify lightweight networking stacks.
David Mapstone
Reference Design
Active Project
This project aims to access the user needs and develop the next increment of capability for nanoSoC. It outlines the justification and motives behind the architectural redesign, design flow improvements and code repository refactor. With a number of new subsystems planned for nanoSoC and learning from various projects to date, this version of nanoSOC is expected to provide a much better support for academic projects.
Reference Design
Active Project
For a chiplet system, you need a communication interface between chiplets. The industry has developed standards that require complicated IPs around UCIe and the CHI interface from Arm. For many academic projects these are probably more complicated than needed . The aim of this project is to produce a simple chiplet communications interface based around the open standard AXI protocol.
The project is hosted here: https://git.soton.ac.uk/soclabs/chiplets/axi-chiplet-controller
Daniel Newbrook
Competition 2025
Competition: Hardware Implementation
Reconfigurable Intelligent Surfaces (RIS) are planar structures composed of large arrays of tunable elements that can dynamically redirect, reflect, or shape wireless signals in the environment.
Zhicheng Shen
