Academic Institution
Logo

People

Research Area
energy harvesting systems, IoT
Role
Lecturer
Research Area
Low power system design
Role
Consultant
Placeholder
Research Area
Physical and Applied Sciences
Role
Research Systems Manager
Research Area
energy-efficient computing
Role
Professor
Name
Research Area
Intermittent Computing, Energy-aware design
Role
Student
Research Area
Machine Intelligence for Nano-Electronic Devices and Systems, Secure and Resilient Hardware Implementation of AI Modules
Role
Postgraduate researcher
Research Area
Machine Intelligence for Nano-Electronic Devices and Systems | Reinforcement Learning
Role
Postgraduate Researcher

University of Southampton

Country
United Kingdom of Great Britain and Northern Ireland (the)
Members icon Members 48
Projects icon Projects 38
Articles icon Articles 8
Contributor since icon Contributor since: Wed, 06/30/2021 - 14:50
AAA icon AAA Member

Actions

Projects

Reference Design
Active Project
Cover image
DRAM Controller integration in megaSoC

To enable full operating system support in megaSoC, a substantial amount of memory is required to accommodate the complexity of modern Linux-based software stacks, including the kernel, drivers, middleware, and user-space applications. Linux environments, unlike lightweight bare-metal systems such as nanoSoC, demand not only larger memory footprints but also consistent access to high-bandwidth memory to maintain performance across multitasking workloads. The most common approach is to incorporate external DRAM, which offers the necessary capacity and throughput.

Collaborative
Active Project
PTP Hardware Clock: Sub-Nanosecond Timekeeping for Chiplet Systems
Introduction

Precision timekeeping is a foundational service in any distributed system. Whether synchronising Ethernet frames to a PTP grandmaster, timestamping die-to-die packet exchanges between chiplets, or scheduling time-critical hardware events, the system needs a clock that is accurate, capturable at multiple points simultaneously, and adjustable by both hardware servo loops and software without stopping.

Collaborative
Active Project
Cover image
NanoSoC Ethernet Subsystem
The NanoSoC Ethernet Subsystem provides an AHB based TCP/IP Offload Engine that provides a SoC system with external Ethernet connectivity without adding the network handling workload to the main SoC processor.
Collaborative
Active Project
AHB Chiplet Communication (Tidelink)
To utilise chiplets for small M-class microcontroller based systems there is a need to extend the range of the AHB standard on-chip bus interconnect. This 'Tidelink' project extends the planned AXI Chiplet controller to support AHB transactions across chiplets.