Hi Fanis,

I've see you've added some update to the architectural design of your project. And at the moment are looking to take in 4 x 8 bit words at a time. One potentially good approach to seeing how you can work on these dot products in parallel would be to use the architecture you've chosen as a starting point (2 parallel calculations of a1, a2, b1, b2) and through simulation see where your current bottleneck are. If the bottleneck is your data processing and not your data fetching, you could try increasing the number of parallel branches until you reach a point where you are able to run the calculations as fast as you can fetch data.

Taking this iterative approach can give you a good view of how to optimise your design for the nanosoc. Also if you take your current design all the way through to synthesis, you can then estimate what footprint a single dot product branch takes up. And estimate how many branches you would be able to fit in the tape out

Daniel

We have developed an over-arching project structure for integration with the NanoSoC. You can find the repository here as well as an example project integrating a AES128 accelerator

In order to use this structure, you will have to fork the "Accelerator Project" repository, and then either clone in your accelerator repository, or add this as a submodule (instructions for this are in the readme). Once you have done this you will have to edit a couple of files. ./env/dependency_env.sh should be edited to add your accelerator directory, and the files in flist/project will need to be updated to add in the files of your repository.

When you have cloned this project structure you should run "source set_env.sh" This will allow you to use the socsim environment. This can be used to run simulation scripts from the simulate/socsim directory.

We are currently updating the documentation but hopefully this is enough to get you started

Here is a good resource for getting started with physical design using the cadence innovus tool. It takes you through step by step from a netlist file to gdsII export.

Hi, Good to see you have resubmited this for the current contest.
Is the sensor frontend going to be an analog subsystem in the SoC or are you planning to use external components for this?
It could be good to get a sense of your design if you could add a block diagram of what you are planning to implement including which components are part of the SoC and what are external interfaces

Hi,
For the ML integration on the SoC bus, with nanoSoC there is a expansion region where you can integrate this, you may want to look some of last years competition projects as most of these were focused on ML/AI, for example:
https://soclabs.org/project/hell-fire-soc

https://soclabs.org/project/fast-knn-hardware-implementation-k-nearest-neighbours-classifier-accelerated-inference

On the APB side, APB is one of Arm's AMBA bus protocols and much simpler than the AHB or AXI protocols. It's used primarily for peripherals that only require low bandwidth and low power which makes it perfect for interfacing with peripheral.
We will soon be working on an example ADC integration in nanoSoC using the APB peripheral bus

Hi Zaheer,

This looks like a very interesting project. I wonder if you might be able to add a bit more detail on what the front end of this looks like?
I'm just wondering what kind of signals you are recieving, are these modulated (and in need of demodulation) or is the aim to have high speed ADC's that can work in GHz range?