milliSoC
Bringing real-world AI hardware to silicon
Designed for small academic and industrial research teams, milliSoC provides a configurable foundation for building application-specific silicon without having to design an entire SoC from scratch. By bringing together programmable processing, dedicated AI acceleration and a flexible system architecture, it enables researchers to focus on their innovations and accelerate the journey from concept to working silicon.
Version 1: milliSoC is under active development, and we welcome collaborations with researchers, industry partners and hardware innovators.
Designed for real-world AI
Modern edge applications increasingly require intelligent processing close to the source of the data. milliSoC is designed to support research and development in areas such as:
- Edge AI and machine learning — efficient inference for embedded and resource-constrained applications.
- Real-time signal processing — high-throughput processing for RF, radar and sensor systems.
- Intelligent vision — low-latency image and video processing.
- Custom hardware acceleration — integration and evaluation of novel research IP alongside programmable processors and AI accelerators.
A flexible, heterogeneous architecture
At its core, milliSoC combines an Arm Cortex-M85 processor, alongside real-time control with an Arm Cortex-R5 and the memory and peripheral infrastructure required for a complete SoC. This SoC includes the optional Arm Ethos-U85 neural processing unit (NPU), for co-processing AI capability, or replace the U85 with your own custom accelerator.
The architecture is designed to be reusable and extensible, allowing teams to integrate their own accelerators, processing blocks and application-specific IP into a working system.
Looking beyond a single chip, milliSoC is intended to support a scalable, multi-chiplet compute architecture. Multiple milliSoC compute elements can work together as a distributed processing platform, supported by dedicated memory chiplets, to explore more demanding AI workloads and new approaches to heterogeneous computing.
From research to silicon
milliSoC follows the SoC Labs philosophy of making custom silicon design more accessible through reusable reference designs, shared expertise and established design flows.
By providing a starting point for system integration, software development and hardware evaluation, milliSoC aims to help small teams reduce the complexity and effort associated with developing their own SoCs.
The platform supports a development path from FPGA-based prototyping towards physical silicon fabrication and evaluation, helping researchers turn innovative hardware concepts into real-world demonstrators.
Collaborate with SoC Labs
milliSoC is being developed as a shared platform for research and innovation. We welcome collaborations with academic groups, industry partners and developers interested in edge AI, real-time processing, custom accelerators and heterogeneous SoC architectures.
Interested in developing your own hardware using milliSoC? Join the SoC Labs community to explore the platform, contribute to its development and help shape the next generation of application-specific silicon.
Reference Design Comparison Table
This table will let you compare this reference design with others on SoC Labs| Title | nanoSoC | milliSoC | megaSoC |
|---|---|---|---|
| Class | Entry | Mid Range | High End |
| Reference Design | nanoSoC | milliSoC | megaSoC/Corstone 1000 |
| Staffing | Single student / academic | Academic + dedicated post-doc | Academic Team |
| Time Scales | 6 months to 1 year | 1+ years | 18 Months - 3 Years |
| Model Forms | small | Real Time | Full Video/Large AI Model |
| Tape Out / Package and Board Costs | From 10k Euro | 25k-50k EUR | >50K - >>50K |
| Processor(s) | M0 | R5 | A53 |
| Processor(s) (speed) | <250 Mhz | 250-800 MHz | 1 GHz |
| Data Rates / On Chip Comms | <2.5 Gbps | 10-80 Gbps | >100 Gbps |
| Data Rates / Off Chip Comms | <50 Mbps | 0.1 - 0.8 Gbps | >1 Gbps |
| On Chip Memory Requirements | 32KB to sub MB | 2 MB+ | 4 MB+ |
| Virtual Prototype Environment | Xilinx ZCU104 | Arm MPS3 | HAPS |
| Tape Out Node | 65nm | 28nm | 16nm |
Related Projects and Workflows
This section details the following: the core reference design, the initial project that led to the definition of the reference design, and any additional projects that extend the reference design for new or additional applications. It also defines the related example workflows for the front end Architectural and Behavioural design stages, and the back end Logical and Physical design stages. Front end Behavioural design are usually accomplished with FPGA environments and tool chains, back end Physical design requires technology specific design rules and EDA tool suites.
milliSoC is a reusable System-on-Chip (SoC) reference platform being developed by SoC Labs to simplify the design and implementation of application-specific processors for real-time embedded systems and edge artificial intelligence (AI). Edge based systems are often characterised by the need for real-time control, interfaces to the real world and the addition of AI. The term Physical AI has been used to describe such systems that can sense, decide, and act in real time.
Daniel Newbrook
Comments
Next Update
Daniel,
Perhaps in your next update you can pick up on some of the points made in the peer nanoSoC reference but flesh out with the specifics associated with milliSoC?
John.
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