Low power design

Designing components and systems with an emphasis on minimizing active (dynamic) and standby (static) power consumption. Increasingly this is addressed by careful logical design of the design in RTL together with companion "power intent", provided as Unified Power Format (UPF) annotation, standardized in IEEE 1801 specification.

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Resources

Reference Manual: Low Power Methodology Manual (LPMM)

Reference Manual: IEEE Standard 1801-2018 for Design and Verification of Low Power Electronic Systems (available to download through the IEEE GET Program)

Projects Using This Interest

Reference Design

Active Project

High bandwidth expansion subsystem block diagram SoClabs

High Bandwidth Expansion Subsystem

Competition 2024

Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage

Competition 2023

Competition: Hardware Implementation

Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks

Known Good Die

University of Michigan

SoC with M3 core in 3D stack solar powered sensor

Known Good Die

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

Pipistrelle-4 65nm low power multi-project SoC

Collaborative

Active Project

Fused: Closed-loop Performance and Energy Simulation of Embedded Systems

Experts and Interested People

Members

Name

Research Area

Precision Data Converters

Role

Analog/Mixed-Signal (AMS) Design Verification Engineer at Analog Devices, Inc.

Name

Research Area

Low power system design

Role

Consultant

Name

Research Area

Neural Networks Acceleration

Role

Research Assistant

Name

Research Area

Design time power estimation using ML

Role

Research staff

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