Low power design

Designing components and systems with an emphasis on minimizing active (dynamic) and standby (static) power consumption. Increasingly this is addressed by careful logical design of the design in RTL together with companion "power intent", provided as Unified Power Format (UPF) annotation, standardized in IEEE 1801 specification.

Explore This Interest

Resources

Reference Manual: Low Power Methodology Manual (LPMM)

Reference Manual: IEEE Standard 1801-2018 for Design and Verification of Low Power Electronic Systems (available to download through the IEEE GET Program)

Projects Using This Interest

Reference Design

Active Project

High bandwidth expansion subsystem block diagram SoClabs

High Bandwidth Expansion Subsystem

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Competition 2024

Competition: Hardware Implementation

Battery Management System-on-chip (BMSoC) for large scale battery energy storage

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Competition 2023

Competition: Hardware Implementation

Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks

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Known Good Die

University of Michigan

SoC with M3 core in 3D stack solar powered sensor

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Known Good Die

Pipistrelle-4 65nm low power multi-project SoC

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Collaborative

Active Project

Fused: Closed-loop Performance and Energy Simulation of Embedded Systems

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Experts and Interested People

Members

Name

AMASSOURI

Research Area

VLSI Digital Circuit Design

Name

Amit Acharyya

Research Area

VLSI systems resource-constrained applications, Low Power Design Techniques, Machine learning hardware design, Signal Processing Algorithm and VLSI Architectures, Digital Arithmetic, Biomedical Devices. AI/ML, Nanoscience & Technology

Role

Professor