Low power design

Designing components and systems with an emphasis on minimizing active (dynamic) and standby (static) power consumption. Increasingly this is addressed by careful logical design of the design in RTL together with companion "power intent", provided as Unified Power Format (UPF) annotation, standardized in IEEE 1801 specification.

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Projects Using This Interest

Competition: Hardware Implementation
Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks
Known Good Die
University of Michigan

SoC with M3 core in 3D stack solar powered sensor
Known Good Die
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Pipistrelle-4 65nm low power multi-project SoC
Active Project
Fused: Closed-loop Performance and Energy Simulation of Embedded Systems

Experts and Interested People


Research Area
Neural Networks Acceleration
Research Assistant
Research Area
Static Memory, Custom Physical Design, Standard Cell Design
Post-PhD Researcher - Adjunct Assistant Professor
Research Area
Machine Learning on Resource-Constrained Embedded Systems
PhD Student


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