Low power design
Designing components and systems with an emphasis on minimizing active (dynamic) and standby (static) power consumption. Increasingly this is addressed by careful logical design of the design in RTL together with companion "power intent", provided as Unified Power Format (UPF) annotation, standardized in IEEE 1801 specification.
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Competition 2024
Competition: Hardware Implementation

Competition 2023
Competition: Hardware Implementation

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Name
Research Area
Static Memory, Custom Physical Design, Standard Cell Design
Role
Post-PhD Researcher - Adjunct Assistant Professor

Name
Research Area
SoC integration and Verification, High Performance low power processor design
Role
Digital Design and Verification Engineer
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