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When creating or editing a…

When creating or editing a skill, how are projects associated? Is the association from the project ?

When is the default debug componentry enough?

This is one of the basic questions for a SoC design. Perhaps a nice worked example of a simple extension to the default configured debug environment for some exemplar targets. With technical manuals they always define the interfaces well but leave the 'fluffy cloud' for where the custom SoC design happens. Adding a worked example of some design in this fluffy cloud would be a useful piece of content to add to SoC Labs and others might also like to add some comment below to share their knowledge.

Tutorial on Principles of Secure Processor Architecture Design

Jakub Szefer from Yale has produced an interesting tutorial on Principles of Secure Processor Architecture Design.

tutorial_principles_sec_arch_20190217 (

True Random Number Generation circuit design

A very interesting presentation on True Random Number Generation circuit design in the first part of this Research Colloquium by Visvesh Sathe, University of Washington

UWECE Research Colloquium: February 4, 2020 - Visvesh Sathe, University of Washington - YouTube



OpenROAD demonstration

A useful video showing the OpenROAD GUI with example use for routing congestion.

Side-channel centric microarchitectural leakage model

An interesting paper from Politecnico di Milan on a framework for extracting a side-channel centric microarchitectural leakage model from in-order CPUs validated using Cortex-M4 and Cortex-M7.

Exploring Cortex-M Microarchitectural Side Channel Information_Leakage

Improved options for cell selection to better match design goals

An interesting paper Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells by Intelligent Systems and Nano-science Research Group at the University of York. It discusses the drive strengths of different standard cells realised through different transistor sizes affecting the current drive capabilities and trade off in area / power. Looks at removing the limiting factor of simple cell selection from known small set to supporting more optimal solutions where EDA tools create cells of exact drive to meet load requirements.

Current EDA tools have limitations in placement of varying geometry cells. The paper introduces a methodology to interpolate fine-grained drive options into the original granularity of standard cell libraries allowing existing EDA tasks to be accomplished but with benefits of more precise cell based optimisation in area / power.

CEID Standard Cell Library from University of Patras

Theodoros Simopoulos from the Computer Engineering & Informatics Department at University of Patras has developed the CEID Standard Cell Library which he has made available for academic use. 

CEID Standard Cell Library (Implemented on UMC 65nm Low Leakage Technology)

Should this item be under the broader FPGA Prototyping topic?

Hi David,

Did you intent this item to be under this?

FPGA Prototyping | SoC Labs

Design Flow information structure


As a community we are going to have to find our way in structuring information in ways that help us all.

The high level and generic design flow stages are traditionally described from Architectural -> Behavioural -> Logical -> Physical ...

Taking these generic flow stages and instantiating them in say a specific FPGA based flow or a specific ASIC fabrication flow and having the environment, tooling, and implementation specifics described in one place is useful.

I suggest we take some inspiration from object orientation in programming models. Perhaps this item ‘FPGA SoC prototyping with Xilinx…’ is a subclass (or derived class) of the more generic ‘FPGA prototyping’ which is a subclass of all specific design flows including for example ASIC flows.

In that case this should be a child of ‘FPGA prototyping’. You can achieve that by setting the relations in the item.

How to set subclass relations

I hope this helps, John.


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