GIC-400 General Interrupt Controller

A Generic Interrupt Controller providing registers for managing interrupts for up to eight Armv7 A class processor cores such as the A7. An AMBA AXI4 slave interface handles message-based interrupts.  It supports the generation of all cores (SPI) and core specific (PPI) interrupts through physical signals.  It generates signals to the wakeup controller and to the processors to indicate that there are valid pending interrupts.

Explore This Technology

Block diagram of GIC 400
Copyright © 1995-2021 Arm Limited (or its affiliates). All rights reserved.

Projects Using This Technology


Interested in this topic? Log-in to Add to Your Profile

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.