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Low-cost 3D die stacking using near-field wireless communication.
This two-tier SoC, fabricated using a TSMC 65nm process, incorporates two Arm Cortex M0 CPU cores in addition to a wireless vertical AHB lite bus for inter-layer power and data transfer. The wireless AHB-Lite bus consists…
The first tape out of the nanoSoC Cortex M0 based SoC Reference Design. This reference design provides a simple microcontroller system appropriate to host and support the development and evaluation of research IP blocks or subsystems. It supports seamless transition from FPGA to physical silicon …
Pipistrelle-4, is the latest in a series SoCs for demonstrating multiple student projects in low-energy systems. Various circuit/system ideas from multiple researcher focusing on energy and performance with optimised SRAM bitcell and low-area overhead energy-efficient flip-flops.
P…
University of Southampton
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United Kingdom of Great Britain and Northern Ireland (the)
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48 |
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38 |
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Contributor since: |
Wed, 06/30/2021 - 14:50 |
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The goal of this project is to design and train a CNN model for spoken digit classification and deploy it on a low-cost system-on-chip (SoC) built around an ARM Cortex-M0 microcontroller with a dedicated CNN accelerator. The SoC will be deployed as a prototype on an FPGA. Its throughput, latency and energy consumption per inference, along with its FPGA resource utilisation, will then be evaluated and compared against other systems.
Melvin Chong Qi Wen
This project focuses on the design and FPGA implementation of a low-power hardware accelerator for a Finite Impulse Response (FIR) filter, intended to reduce noise in speech signals before speech recognition. The accelerator uses a 32-tap, 16-bit serial multiply-accumulate architecture that reuses one signed multiplier and one accumulator to reduce hardware cost and energy consumption. The FIR algorithm is verified using a MATLAB model and RTL simulation.
Shiva Sangati