Physical Design

 The OpenROAD flow
An example flow by OpenROAD, https://theopenroadproject.org/

In physical design, various stages of processing refine the abstract logical design, as represented by the gate-level netlist, into the final geometric layout of the GDSII file that is needed for foundry fabrication. The GDSII file contains a database of geometrical design information consisting of many layers of geometrically defined objects that are used to create the pattern masks needed for IC fabrication. 

The design flow uses various tools and files during the stages of processing to optimise the placement of items in the netlists and the routing of interconnections between them without breaking any of the design or manufacturing constraints. 

Although viewed as a sequence of stages of refinement from abstract logical design to final layout, the activity is usually as number of iterations of the Physical Design processes, each optimising the physical design towards certain design goals based on power, performance, area, etc.

 

The major Electronic Design Automation tool vendors have various tools to support the Physical Design flow stages. The OpenROAD project is developing a fully autonomous, open-source tool chain for digital layout generation with an initial focus on the RTL-to-GDSII phase of system-on-chip design. The aim is to implement automated flows using integration of machine learning, problem partitioning and decomposition, and parallel/distributed search and optimization.

Tool chains support varies proprietary or open file formats for intermediate results. 

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Research Area
Wireless power transfer, energy harvesting, amplifier, filters, antennas
Role
Senior Lecturer

Related Project Milestones

Project Name Target Date Completed Date Description
Battery Management System-on-chip (BMSoC) for large scale battery energy storage Physical Design
  1. Analog Design
    a. Physical layout and verification
    b. Post layout simulation
  2. Digital Design
    a. Synthesis
    c. Floor Planning
    b. Place and route
    c. Functional verification

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