By a range of verification tasks test the logical representation of the system. Verification can be by formal (mathematically correct) methods, generated tests and manually created tests. Logical Equivalence Checks are performed against higher level RTL level model descriptions.
Gate level verification can be used to ensure the Synthesis translation was correct and the design has not been altered or affected. It also tests low level entities such as power structures that are not represented in RTL descriptions and added during synthesis. Gate level verification use simulations operating on gate level netlists. Verification at this level is not usually exhaustive due to the time required to run such a gate level simulation. Test vectors are prioritised, for example specific timing concerns not covered by Static Timing Analysis.