Clock Tree Synthesis starts the process of signal routing considering the most time critical signals. The aim is to distribute the clock signal to all the design elements to avoid skew and minimise latency.

The work involves both clock tree building and clock tree balancing. There are various structures for clock trees, H and X shapes, fishbone, spines, etc. and can have multiple decompositions. Clock tree inverters are placed equidistant to keep the pulse widths symmetrical to ensure edge triggered events. Balancing a tree involves adding clock tree buffers (CTB) for clock skew reduction. 

Like other physical design activities the amount of design effort depends on the complexity and constraints of the overall SoC design. The clock network in a SoC design can be a significant consumer of power. Careful use of clock tree inverters and buffers minimises area and power demands.

The performance of the clock network is likely to vary with temperature, meeting timing closure under some conditions but not others. Like other steps in the physical design flow it is likely iterations of design may be required, especially if SoC design constraints are tight.  The H-tree shape provides a natural routing symmetrical structure that minimizes skew that can aid stability over temperature ranges. Maintaining the routing of the H-tree shape can be complicated by placement of large memories and other macros and may need manual intervention to adjust EDA tool algorithm selection of tree structures to maintain design constraints. 

Complexity of the SoC design will determine if standard automated clock flow can be maintained. Each EDA tool provider has clock tree design strategies and optimisations that reduce power, improve performance or reduce area and other design objectives.

The outputs are Design Exchange Format (DEF), Standard Parasitic Exchange Format (SPEF), and Netlist files.