Clock Tree Synthesis

Clock Tree Synthesis starts the process of signal routing considering the most time critical signals. The aim is to distribute the clock signal to all the design elements to avoid skew and minimise latency.

The work involves both clock tree building and clock tree balancing. There are various structures for clock trees, H and X shapes, fishbone, spines, etc. and can have multiple decompositions. Clock tree inverters are placed equidistant to keep the pulse widths symmetrical to ensure edge triggered events. Balancing a tree involves adding clock tree buffers (CTB) for clock skew reduction. 

Like other physical design activities the amount of design effort depends on the complexity and constraints of the overall SoC design. The clock network in a SoC design can be a significant consumer of power. Careful use of clock tree inverters and buffers minimises area and power demands.

To perform timing analysis, the tool needs information about the timing characteristics of the logic cells used in the design.

The performance of the clock network is likely to vary with temperature, meeting timing closure under some conditions but not others. Like other steps in the physical design flow it is likely iterations of design may be required, especially if SoC design constraints are tight.  The H-tree shape provides a natural routing symmetrical structure that minimizes skew that can aid stability over temperature ranges. Maintaining the routing of the H-tree shape can be complicated by placement of large memories and other macros and may need manual intervention to adjust EDA tool algorithm selection of tree structures to maintain design constraints. 

Complexity of the SoC design will determine if standard automated clock flow can be maintained. Each EDA tool provider has clock tree design strategies and optimisations that reduce power, improve performance or reduce area and other design objectives. The tool outputs are Design Exchange Format (DEF), Standard Parasitic Exchange Format (SPEF), and Netlist files.

Cadence

Clock tree synthesis

The Cadence tools offer . 

Timing Analysis

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Synopsys

Design Compiler, IC Compiler II, and PrimeTime share common timing analysis features and use the similar commands to specify timing constraints and generate timing reports. These commands are known as the Synopsys Design Constraints. As you use the tools and specify additional parameters the tools build up a set of constraints on the design that ensure it will operate when fabricated. 

Clock tree synthesis

Clock tree synthesis is undertaken within the IC Compiler II tool. 

Timing Analysis

The PrimeTime tool within IC Compiler II can be used to verify that the SoC design will work at the intended clock speed. It provides signoff timing analysis capability to check all possible paths for timing violations.