Tape Out

Tape Out is the hand over point from the SoC design flow to the physical device fabrication flow. It is usually the point where the design is passed from the designers to the wafer production facility. There may be an intermediate step if the design is to be combined with others as part of a Multi-Part Wafer (MPW) service. 

One of the key aspects is translating the final design into mask sets used in the key part of the fabrication process, the photo-lithograpy steps that pattern the wafer to build up the features that make the functional devices. The skills with Tape Out involve using Computer Aided Design software to inspect and qualify the many layers of circuit/device design which are made into masks. As well as checking before submission that none of the wafer foundry rules have been violated. The work may need to respond to issues identified in checks at the foundry that could cause potential problems in manufacturing the design.

Potential considerations include:

Tapeout Flavour

This is particularly crucial for designs that are fabricated using a mini ASIC foundry service to ensure that the correct metal stack is used as well as any other options the foundry supplies to support your design. Mini ASIC runs are usually placed on the same wafer for fabrication, the foundry have to ensure that all of the designs submitted confirm to the foundry requirements. Information on this is usually supplied with the foundry Process Development Kit.

Packaging Requirements

It may be necessary to place a marker to indicate the known position of a pin (normally pin 1) or to easily identify the orientation of the die. This is to allow the wire bonding or other attachment method of the die to the package to be completed in the correct orientation. This requires space and needs to taken into account in the layout. Such a marker will need to fit within the design rules of the technology. 

Projects Using This Design Flow

Experts and Interested People


Research Area
Low power system design
Research Area
Machine Learning on Resource-Constrained Embedded Systems
PhD Student

Related Project Milestones

Project Name Target Date Completed Date Description
Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Tape Out

Submit for tapeout to europractice TSMC 65nm mini ASIC shuttle


Log-in to Add to Your Profile


Add new comment

To post a comment on this article, please log in to your account. New users can create an account.