This area focuses on the design flow steps necessary to take a System on Chip design from initial concept to final implementation. The design flow for any project spans the four high level generic stages, each describing the steps that need to be completed when developing a SoC design. The example flows section describes specific flow/tool implementations showing different ways to implement a flow unique for your project.

You can use the navigation scheme above for a tree view of the design flow steps with more detail of each step.

We are always looking to add additional resources and references to community work in the various design flow steps. We hope members will declare themselves as 'Experts' or 'Interested People' and also recommend non-members they know have expertise or interest. We are looking to appoint Moderators from within the community to help ensure the accuracy of material in each area, if this interests you please then let us know.

Name Description Resources
Architectural Design

The concept of reusable design patterns is familiar to many disciplines. At SoC Labs we are interested in reusable design patterns incorporating Arm based components with parts that are unique to your specific research challenge.

Specifying a SoC

Requirements

Getting Requirements

IP Selection

A SoC design is likely a selection and configuration of Arm IP (using tools such as Socrates) to define the main architecture with specific blocks either developed uniquely or existing third party blocks modified or arranged i

Universal Verification Methodology

The Universal Verification Methodology (UVM) is a standard to create a modular reusable generic verification environment. It aims to reduce the effort of reusing IP by making it easier to reuse verification components associated with the IP.

Behavioural Design

Takes an Architectural Model and creates a full behavioural description of a system that can be run in simulators or transformed into a technology independent register-transfer level (RTL) description.

Behavioural Modelling

Creation of a "Behavioural Model" of the system consisting of behavioural blocks each described with a high level description language.

Simulation

Supports activities including, analysis of system behaviour including timing, execution of tests to validate the system model and in some cases develop and debug software that will operate in the system. 

Generate RTL

Creation of a independent register-transfer level (RTL) description of the system consisting of registers and data flows from a hardware description language (VHDL, Verilog, etc.).

RTL Verification

Is a 'design closure' stage to ensure independent register-transfer level (RTL) description of the system is consistent.

Logical Design
Technology Selection

Fabrication/deployment of a SoC requires selecting a specific technology that the independent register-transfer level (RTL) design can be transformed into a technology dependent form that can be passed to a fabrication house for manufature, deployed on a prefabricated logic such as a Field Progra

Standard Cell Libraries

Standard Cell libraries help simplify the design task by abstracting some of the complexity of physical transistor layout and local connection while still understanding the design tradeoffs to meet the system level goals for power, area, and performance for a system-on-chip (SoC). 

Memory generators

In any SoC design memory makes up a significant portion of the transistor count and area. Small memories can be synthesized using flip-flop or latch standard cells, but synthesizing large memories is inefficient in area, energy, and timing compared to using custom bits in a memory block.

Synthesis

Is the process step to transform the technology independent register-transfer level (RTL) description of a system into a technology dependent netlist using a specific technology cell library.

Design for Test

Modify the functional design of the system to add logic to allow control over the system while under test or to allow the observation of operation of the system. Additional circuit elements or probe points can be driven by external test environments including automated test equipment.

Logical verification

By a range of verification tasks test the logical representation of the system. Verification can be by formal (mathematically correct) methods, generated tests and manually created tests. Logical Equivalence Checks are performed against higher level RTL level model descriptions.

Physical Design

In physical design, various stages of processing refine the abstract logical design, as represented by the gate-level netlist, into the final geometric layout of the GDSII file that is needed for foundry fabrication.

Floor Planning

Optimises the placement of all the components, connection pads, macros, standard cells, power, ground, etc, taking account of physical constraints such as minimal area, separation, interconnect lengths, power as well as timing and other considerations.

 

Clock Tree Synthesis

Clock Tree Synthesis starts the process of signal routing considering the most time critical signals. The aim is to distribute the clock signal to all the design elements to avoid skew and minimise latency.

Routing

Depending on the fabrication technology selected the number and capacity metal layers available for routing all the interconnections for a design varies making routing layout a complex 3-dimensional problem.

Timing closure

Timing closure completes the process of adjusting all the design elements and the signal paths between them to meet the overall system timing requirements.

Physical Verification

Physical design activities require verification based on physical models based physical quantities.  As physical design activities progress the developing design needs to checked to ensure the activities have not caused any change to the higher level design.  

Tape Out

Tape Out is the hand over point from the SoC design flow to the physical device fabrication flow. It is usually the point where the design is passed from the designers to the wafer production facility.

Example flows

This section on design flows contains  example flows with information on specific flow/tool implementations.

Accelerator Wrapper Flow

In order for an accelerator to be integrated within an SoC, the accelerator needs to share interfaces with the system. In the case of NanoSoC, this utilises an AHB-lite bus.

Continuous Integration and Deployment for verification

Continuous Integration and Deployment is a project development technique to merge code changes from a project team into a central repository where automated build and testing are used to find any system integration issues and provide versions of the project for continued development an fixes issu

FPGA SoC prototyping with Xilinx(R) PYNQ(R) platform

FPGA prototyping a System-on-a-Chip design enables the hardware design to be tested at or near real-time and software development to be started while the SoC implementation, verification, fabrication and packaging proceed in parallel.

SoC Design Contest 2023 example flow

SoC Labs and Arm have announced a joint 'Bridging the Skills Gap' SoC Design Contest that will run during 2023. This example design flow is provided to help groups engage with the contest.

Getting Started

In Getting Started with your SoC design you will need to pull together information on the various aspects of hardware design that support your project.

Project Structure

Maintaining a good structure for a Project helps bring together the various aspects of Technology IP, the Design Flow tools and all their interactions, files the generate, etc.

IP Library Structure

It is important to structure your external IP well on your local system/network for a magnitude of reasons. The first is that external IPs can be quite large and is something you may not wish to have stored on a Git server.

Specifying an Accelerator

As part of the Architectural Design phase and Accelerator Design Flow, before writing any behavioural design it is important to try and specify the accelerator that you intend to make.

Accelerator Design Flow

Accelerator SoC Design Flow

Algorithmic Modelling Design Flow

One of the first stages of the behavioural design stage of a project is to produce a time-independent algorithmic model which can represent the operation of the accelerator.

Basic System Accelerator Integration Verification

A large part of the behavioural design phase of a project is actually the verification of the design at multiple levels of abstraction.