Depending on the fabrication technology selected the number and capacity metal layers available for routing all the interconnections for a design varies making routing layout a complex 3-dimensional problem. As with other stages, design rules, routing algorithms and other layout design constraints are managed in EDA tools.  

There is much ongoing and historic research into how to optimise routing but it is a non-trivial.  All EDA tools restrict the routing problem in terms of allowable layout of the wires, the use of vias between layers, minimising options to reduce potential for crosstalk or other radiation concerns, as well as many other design constraints. Tools are often challenged to find a compromised routing let alone an optimal routing. 

In routing the layout polygons of the pins (or terminals) of the cells (circuit components in the netlist) have layout formed for the physical connections (wires) between them based on the logical connections in the netlists. The routing activity completes all the necessary interconnections between components in 2 stages, Global routing locates interconnects aiming to minimise the area used while Detailed routing aims to minimise interconnect lengths.  

The use of macro blocks and consideration of the specific Input/Output needs of a design, as well as other placement decisions can have an impact of routing options. Analysis of placement density and area utilisation can allow routing to come to an acceptable layout  with fewer iterations. The tighter the set of constraints on the design the more involved the potential routing issues. 

Routing must ensure the design is 100% connected with no layout versus schematic violations (the layout faithfully represents the logical design) and no open or shorted paths. Signal Integrity violations can be mitigated by specifying critically sensitive nets to potential crosstalk and electromagnetic interference/compatibility concerns. This is the case for high speed, clock signal, or sensing data paths and locations close to Input/Output near the pad ring. All the metal interconnections must meet the foundry requirements, as defined in the design rule checks in the technology Process Development Kit. Design rules can vary from layer to layer. All signals paths need to meet their timing constraints. Power paths should not have any voltage or current density concerns. Many additional constraints are considered in coming to an acceptable routing that ensures fabrication and life time performance of the devices fabricated to the design.

Projects Using This Design Flow


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