Logical Design

This page outlines the steps needed to complete the Logical design stage. Logical design is the process of taking the technology independent RTL abstraction of your design and converting it into an technology-mapped gate implementation.

Technology Selection

An abstract RTL design can be translated into any variety of execution forms, that can be passed to any number of fabrication houses for manufacture into ASICs. As well as choosing a fabrication (for example based on cost, timescale, performance, etc.) a comprehensive library needs to be assembled of technology components such as standard cells, specialist memory macros and other hardened physical IP macros such as PLLs which the tools will understand to build up timing annotated gate-level netlists.

Synthesis  

There are a number of tools that support the process of logic synthesis, some open-source such as Yosys and OpenRoad and others from industry EDA vendors, such as Cadence Genus and Synopsys DC. The stage is similar to the FPGA synthesis step used in the preceding Behavioral Design stage. In that stage, the RTL representation was converted into a representation of netlist of logic gates, flip-flops, look-up tables (LUTs), that can be executed on the FPGA. Here the RTL is converted into a representation that will be fabricated as an ASIC.

It is very likely that a project will need to iterate a number of times the Synthesis stage. In an initial iteration, the RTL may be mapped to a standard cell library of generic cells, later iterations may use different foundry variants of technology node specific cells depending on specific Power, Performance, Area requirements. Another iteration may be used to add specific Design for Test functionality such as inserting scan-chains, while other iterations may be used to perform more advanced levels of logic optimisation supported by various tool options. 

Once the netlists, usually in verilog, are output the tool should also create a new set of design constraints as well as design databases (.DDC files in case of Synopsys DC) and a set of timing and area report which can be customised depending on the needs of the project flow.

Design for Test

In this phase of the design process the functional design of the system is enhanced to add non-functional logic to allow control over the system while under test conditions. This logic adds external visibility and control of the functional logic to allow exercising of known logic paths to a design such that it can be tested once manufactured. 

Logical verification

The technology-mapped netlist can now be verified. 

Gate-level simulation 

One option is to use tools that act a simulators of the technology gate functions based on charaterisation data from the specific foundry. With gate-level simulation (GLS) it is possible to verify that the same RTL level tests still pass on the synthesised gate-level logic netlist. 

Logic Equivalence Checking

Common industry practice today is to not use GLS and instead use Logic Equivalence Checking tools such as Synopsys Formality. Such tools use formal methods to be able to prove mathematically that the logical function of the RTL abstract representation and the technology dependent netlists are equivalent.

Phase Exit

Once verification is confirmed, you can pass over the design outputs to the Physical Design phase.

More details on each step can be found in the pages for each outlined below.