Standard Cell libraries help simplify the design task by abstracting some of the complexity of physical transistor layout and local connection while still understanding the design tradeoffs to meet the system level goals for power, area, and performance for a system-on-chip (SoC).
Standard Cell libraries are a collection of well characterised basic circuits that Electronic Design Automation (EDA) tools use to instantiate the larger design based on the design constraints (optimisation choices, timing, etc.). Characterisation of the cells is critical to obtaining realistic estimates of post layout performance that will be close to those of the final fabricated devices. The description of each cell includes layout, perfance and other characterization data (slew, delay, capacitance, drive strength, etc.) in the form of look-up tables needed by the EDA design tasks to allow selection of the best standard cell candidates to optimise the final design.
Cell area is usually defined in terms of height in tracks, a track being the space needed to draw the smallest metal connection (with appropriate spacing). For example, a standard cell of 9T (nine tracks high) might have a 12T derivative for higher performance and a 7T derivative for minimal area. The internal layout and resulting characteristics comprimised for the different power, area, and performance trade off. Selection cannot be variable at every possible location. To ensure cells are places without causing design rule violations, while enabling routing of power and ground between adjacent cells in a row, the height of cells and the arrangement of elements at the edge of the cells is tightly defined.
The cell layouts are made to assist the EDA physical design tasks such as Place and Route. As technology nodes get smaller the information requirements for both standard cell definition and characterisation and EDA design tasks becomes more involved to meet the more exacting needs of the more complex fabrication methods involved.