Generate RTL

Creation of a independent register-transfer level (RTL) description of the system consisting of registers and data flows from a hardware description language (VHDL, Verilog, etc.).

The process usually involves use of an High Level Synthesis Compiler to translate the high level language description of the untimed or partially timed model of the system to an RTL description. The RTL implementation can be optimized for objectives such as power, performance, and area.

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Experts and Interested People

Members

 
Name
Meet Sangani
Research Area
HIgh speed design
Role
Researcher

Related Project Milestones

Project Name Target Date Completed Date Description
Battery Management System-on-chip (BMSoC) for large scale battery energy storage Generate RTL
  • RTL design and behavioural simulation of the battery state monitoring methodology.
  • Synthesis and FPGA implementation of Hardware software codesign on Zedboard (Zynq-7000 SoC).

 

 

 

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