Generate RTL

Introduction

Creation of a Register Transfer Level (RTL) abstract description makes it possible to design and verify large synchronous digital systems such as System on Chip designs that can be require a very large number of transistors. RTL offers a higher level of abstraction for design than the basic logic gates that perform Boolean functions of a physical design. As RTL is abstraction from gates it is limited to models that obey the mathematics of Boolean logic. An Register Transfer Level (RTL) abstract description of the system simplifies translation to the gate level and final physical implementation of the System on Chip.

Using RTL as an abstract description of the system

A system is decomposed into functional blocks in an RTL description consisting of registers and data flows. Registers are the basic building blocks, they can act as a data store and  synchronize operation to edges of clock signals. Registers hold the inputs, outputs, and intermediate results of any combinational logic operations that make up the function of a block within the system. Smaller blocks perform operations that are Arithmetic doing mathematical calculations on data in registers or Logical doing bit level operations on data in registers. These operations are defined in the hardware description languages such as Verilog and VHDL.

Many introductory tutorials to RTL design use a simple logic block as an example but designers tend to work in higher level primitives, such as multiplexors, multipliers, or even large functions of a system that are often added as a hard macro that hides the internal RTL representation as a way of protecting it from being corrupted or for commercial IP protection. Arm originally offered it's system IP to academics in this hard macro form but the Arm Academic Access programme now makes it available for academic use in RTL form. 

The design task is then to specify all the operations to be performed and the flow of data between registers to implement the functions of the system. 

Generating the necessary RTL

Parts of the RTL description of a system are generated in different ways. Some parts are imported such as large block and macros. High Level Synthesis is a method to translate models described in higher level abstraction languages of untimed or partially timed models of parts of the system into an RTL description. Some parts are written by engineers to integrate the complete system design in hardware description languages (VHDL, Verilog, etc.). A project will consist of many separate files of RTL which are integrated ensuring all the connections between the various parts are made. 

Optimising the model

The RTL implementation can be optimized for objectives such as power, performance, and area.