Synthesis

Is the process step to transform the technology independent register-transfer level (RTL) description of a system into a technology dependent netlist using a specific technology cell library.

Most Electronic Design Automation Synthesis tools support translation from designs written in SystemVerilog, Verilog, VHDL or a mixture of them. 

Synthesis can be defined to optimise the output for different criteria, for example area use, timing, allowable loads on signals, the movement or merging of registers, or to control the amount of time a synthesis takes. Synthesis attributes and directives can be included in the source, for example to direct the synthesis to perform or not certain actions when synthesizing a design. Synthesis Attributes, such as expected arrival time of a signal at an input port, and Constraints, such as maximum input to output delay, are added to direct the synthesis.

Synthesis can be initiated from within an Integrated Design Environment by the designer or via a command interface that can be used to make scripts and automation of the process.