RTL Verification

Is a 'design closure' stage to ensure independent register-transfer level (RTL) description of the system is consistent.

High level languages have constructs to aid the verification process, these generate the stimuli that are used to verify the RTL design descriptions in a simulation tool.

 

Projects Using This Design Flow

Collaborative
Active Project
dflynn-University of Southampton

Arm Cortex-M0 microcontroller
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Experts and Interested People

Members

 
Name
Meet Sangani
Research Area
HIgh speed design
Role
Researcher

Related Project Milestones

Project Name Target Date Completed Date Description
Battery Management System-on-chip (BMSoC) for large scale battery energy storage RTL Verification

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