RTL Verification

Introduction

Is a 'design closure' stage to ensure independent register-transfer level (RTL) description of the system is consistent and ready for later stages of the design process.

Methods of Verification

The RTL description of the system can be deployed to an FPGA.

If a formal method approach is being used for the behavioural design task then proofs can be generated that show the design matches the specification for the system.

The RDL can be verified using  test benches in a simulator environment. High level languages have constructs to aid the verification process, these generate the stimuli that are used to verify the RTL design descriptions in a simulation tool.