RTL Verification
Is a 'design closure' stage to ensure independent register-transfer level (RTL) description of the system is consistent.
High level languages have constructs to aid the verification process, these generate the stimuli that are used to verify the RTL design descriptions in a simulation tool.
Projects Using This Design Flow
Collaborative
Active Project

Experts and Interested People
Members
Actions
Add new comment
To post a comment on this article, please log in to your account. New users can create an account.