IP Selection

A SoC Labs project is likely a selection and configuration of Arm IP to define the core of the system architecture with additional specific blocks either developed uniquely as part of your project or based on existing third party blocks modified or arranged in a novel way. If used systematically, such reuse of design patterns increases both the quality of the SoC and the productivity of teams developing them, leading to shorter design times. The SoC Labs reusable reference designs are based on one of the Arm defined Corstone subsystems as these provide the core compute subsystem for the SoC design. The subsystems can be configured for different application needs perhaps using tools such as Socrates .

The Arm IP available under the Arm Academic Access programme is listed in the technology section of this SoC Labs site. We also encourage academic groups to add their IP to the technology section to help others in the community. The technology section aims to be a place where you can find information on both the Arm IP available freely to the academic community and also additional IP that the academic community has developed. 

As part of the Architectural Design phase as well as outlining the requirements for any unique IP it is important to try and specify the IP that you intend to reuse. This allows you to consider a number of factors that you will need to define in order to implement your IP in hardware. You may not know all of the specified parameters at the start of your project, but it is good to keep them in mind as you develop your IP, and commit the implementation in hardware.

The specification process for both digital IP and analog/mixed signal IP follow similar flows but the details of each step are different. Please expand the corresponding sections below to read further on the specification of your IP.

NanoSoc reference design

NanoSoC is a simple microcontroller based SoC design for evaluation of academic developed research hardware such as a custom accelerators or signal processing sub-systems. It extends the Arm Corstone 101 subsystem which defines the main architecture for the overall SoC system design. The processor is the Cortex M0 which has a a low gate count and small area making ideal for low cost tape out for PhD and Masters student projects. The reference design includes options to efficient data movement through the system using either the simple ow gate count DMA 230 engine or the high performance DMA 350 engine. 

Analog/Mixed Signal IP 

 

MegaSoC reference design

MegaSoC is a application processor based SoC design capable of running a Linux operating system. Systems for complex tasks such as autonomous vehicles, robots, smart phones, etc. require complex application processor based design. It extends the Arm Corstone 1000 subsystem which defines the main architecture for the overall SoC system design. The compute subsytem combines a host processor, the Cortex A53 which implements the 64-bit Armv8-A architecture with TrustZone and Secure Enclave for added system security with two optional Cortex®‑M, or other compute systems. It is a complex SoC design for large research projects.