FPGA SoC Prototyping design flows

This section outlines the FPGA SoC Prototyping design flows that are being used to support SoC Labs projects. There are a number of SoC design environments available and these examples are not an exhaustive survey of FPGA design environments. Hopefully the community will add additional FPGA SoC Prototyping design flows as more projects develop. 

Vendors of FPGA prototyping environments have a variety of product offerings and points of differentiation but consist of the Field Programmable Gate Array (FPGA) hardware and associated design tools. FPGA environments are use in academic settings as the final deployment system for a project but these example flows are for prototype design activities within SoC Labs design flow leading towards an ASIC tape out. 

SoC Labs projects can use one of the re-usable reference designs or a unique design based on the IP available  under Arm Academic Access. 

It is important to have adequate resources with the FPGA hardware to configure the SoC design. SoC Labs projects vary in the scale of design complexity and require different FPGA hardware to support them. The optimal amount of FPGA resource and the kind of FPGA resource is dependent on project. Some projects may require logic, some significant communication or input/outputs. Each vendor has slightly different ways to describe resources but they are made up of:

• Logic resources (LUTs, Flip-Flop, etc.)
• Memory resources (Distributed RAM, Block RAM, etc.)
• Clock resources (PLL, etc.)
• Input/Outputs (varying transmission rates and transceivers) 
• DSP slices

FPGA hardware can also include dedicated hard IP blocks for specific purposes such as Memory Controllers and a variety of CPU cores including the arm processor range. The later are often described as a Processing System (PS) where as the configurable resources as described as the Programmable Logic (PL). These can be very useful for quick prototyping, especially hardware/software co-design, but as the SoC design moves further down the design flow to ASIC tape out these hard cores have to be replaced by the actual IP blocks required for tape out.

The SoC Labs reference designs avoid reliance on hard IP cores and the Processing System (eg. Zynq) to ensure that all the IP can be verified, the RTL is synthesizable, and is functional for ASIC tape out. A project also need to verify the communication of the SoC design and it can boot correctly once fabricated.
Our approach to SoC prototyping in FPGA is to instantiate the entire SoC and connect to the various communications channels and GPIO using a test socket in FPGA. In the Pynq environment this means you interact with the SoC from a software environment. 

Below shows the SoC Labs reference designs and the corresponding FPGA resources and development boards that have been verified. The FPGA prototyping environment can become constrained as the FPGA resources get saturated so it is sensible to plan for additional contingency when choosing an environment.

FPGA Technology options

• nanoSoC 
  • x LUTS xBRAM
  • Confirmed boards: Xilinx ZCU104, Pynq Z2, Kria
• milliSoC (under development)
  • x LUTS xBRAM
  • Proposed boards: Arm MPS3, Xilinx KCU105
• megaSoC (under development)
  • x LUTS xBRAM
  • Proposed boards: HAPS SX

FPGA design flow

FPGA prototyping a System-on-a-Chip design enables the hardware design to be tested at or near real-time and software development to be started while the SoC implementation, verification, fabrication and packaging proceed in parallel.