Behavioural Modelling

Creation of a "Behavioural Model" of the system consisting of behavioural blocks each described with a high level description language.

Projects Using This Design Flow

Competition 2024
Competition: Collaboration/Education

IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL.

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Reference Design
Active Project
High bandwidth expansion subsystem block diagram
SoClabs

High Bandwidth Expansion Subsystem

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Collaborative
Request of Collaboration

Event-B to FPGA process flows

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Experts and Interested People

Members

 
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Name
Peter Wilson
Research Area
Mixed Signal IC, Power Electromics, Silicon Photonics, Digital IC, Verification
Role
Professor

Related Project Milestones

Project Name Target Date Completed Date Description
Battery Management System-on-chip (BMSoC) for large scale battery energy storage Behavioural Modelling

  1. Analog Design
    a. Identifying the PDK for reaching the HV requirement of the sensing front-end part
    b. Analog/Mixed signal block design partitioning and Verilog AMS model generation



     
IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL. Behavioural Modelling

abstract representation of the system 
ADC Integration in nanoSoC Behavioural Modelling

Model the analog behaviour of the subsystem and confirm it meets the requirements

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