Behavioural Modelling

Creation of a "Behavioural Model" of the system consisting of behavioural blocks each described with a high level description language.

Projects Using This Design Flow

Competition 2024
Competition: Collaboration/Education

IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL.

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Reference Design
Active Project
High bandwidth expansion subsystem block diagram
SoClabs

High Bandwidth Expansion Subsystem

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Collaborative
Request of Collaboration

Event-B to FPGA process flows

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Experts and Interested People

Members

 
Profile picture for user Son Hoang
Name
Son Hoang
Research Area
Formal System Development
Role
Lecturer
 
Name
AMASSOURI
Research Area
VLSI Digital Circuit Design
 
Profile picture for user John Colley
Name
John Colley
Research Area
Formal modelling
Role
Researcher

Related Project Milestones

Project Name Target Date Completed Date Description
IMPLEMENTATION OF FIXED TIME BASED TRAFFIC LIGTH SYSTEM USING FPGA WITH VERILOG HDL. Behavioural Modelling

abstract representation of the system 
ADC Integration in nanoSoC Behavioural Modelling

Model the analog behaviour of the subsystem and confirm it meets the requirements

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