Floor Planning

Optimises the placement of all the components, connection pads, macros, standard cells, power, ground, etc, taking account of physical constraints such as minimal area, separation, interconnect lengths, power as well as timing and other considerations.


The floor plan needs to take into account any external constraints in terms of the expected pacakging of the SoC design.

Projects Using This Design Flow

Experts and Interested People


Related Project Milestones

Project Name Target Date Completed Date Description
Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Floor Planning
ADC Integration in nanoSoC Floor Planning

Floor planning and layout of the subsystem


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