It would be good to see you plan out your initial milestones. You can follow some of the generic design flow stages or define your own.

The generic flow Architectural Design stage currently has three sub-stages:

1. Specifying a SoC

   Work through the items needed to specify the highest level of design for the SoC. Daniel above asks some for a block diagram which always helps convey your design.

2. IP Selection

   Pick the IP parts from the Technology section. You have listed the main M0 processor IP. What IP will you adopt for other functions, eg. will you use the PL011 UART IP block and will you adopt the APB bus? You might also want to think about your Project Structure and other high level Design Flow considerations.

3. Verification

   You should start to think about how you will validate your SoC design. Creating verification and validation assests as you develop the design is a good working practice.

You should find some helpful examples from some of the other SoC Labs projects.

Happy to help and answer any questions.

Thank you for your initial milestone of  SoC Hardware Design. You had a target of the end of April How did that go?

I see this initial milestone to be much like the generic flow Architectural Design stage which currently has three sub-stages:

1. Specifying a SoC

   So this is aligned to your 'aim to define the hardware used in the SoC'. I think will also help to think about the data rates and flows through the system. 

2. IP Selection

   Pick the IP parts from the Technology section. You have listed the main M0 processor IP. What IP will you adopt for other functions. I was interested to hear that you had 'written in Verilog to allow protocol conversion between AHB Lite protocol used in ARM Cortex M0 and UART/I2C peripheral' . Do you plan to use the PL011 UART IP block and adopt the APB bus? or are you taking a different design plan? 

   You might also want to think about your Project Structure and other high level Design Flow considerations.

3. Verification

   You should start to think about how you will validate your SoC design. Creating verification and validation assets as you develop the design is a good working practice.

You should find some helpful examples from some of the other SoC Labs projects.

Happy to help and answer any questions.

Here is a good example of update to a milestone to add a completion date and show progress. It comes from one of last years projects.

It shows both the Completed Date and key additional information such as the reported area with a clear statement of the inputs that this is not using a specific technology node standard cells.

Although the actual work of Integration with nanosoc comes later in the milestone I feel we should complete the Architecture definition as soon as we can. This will help contestants in the educational/collaboration track with their own Architecture definitions.

Daniel has now published a mixed signal subsystem reference design project to extend the nanosoc reference design to add analog to digital conversion using the APB peripheral bus.

Hopefully this will help you with your Architectural design.

Can you help define what type of  photoplethysmograph (PPG) sensor you intend to attach to the SoC. 

Daniel has now published a mixed signal subsystem reference design project to extend the nanosoc reference design to add analog to digital conversion using the APB peripheral bus.

Hopefully this will help you with your Architectural design.

Hi,

It would be helpful to understand a little about your proposed sensor gateway.

Daniel has now published a mixed signal subsystem reference design project to extend the nanosoc reference design to add analog to digital conversion using the APB peripheral bus.

Hopefully this will help you with your Architectural design.

If you would like to let us know any specific plans for a SoC design that might be interesting then we can see what we can do in collaboration. A good way to start is to either link to a project or declare some technologies or work flow stages that you are looking to develop.

Daniel has now updated the mixed signal subsystem reference design project, you might want to follow that project to help you in your own Architectural Design.

Daniel has now updated the mixed signal subsystem reference design project, you might want to follow that project to help you in your own Architectural Design.