Use the Tabs below to find information on community projects. Project pages have links to the 'technology' and 'design flow' stages used and ways you can comment on or join a project.
- Projects are key to community hardware design
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As a community hardware design activity we form our collaborations around shared design actions making Projects a core of the SoC Labs community. Projects help us share and reuse hardware and software developments around core Arm IP to help us in our research goals.
- A project, takes technology and uses a design flow to make a SoC.
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A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of a system. Any System On Chip usually involves the use of pre-existing IP blocks. A project team can select IP from the technology section of the site during the first stage of a design flow, Architectural Design. Later stages in the design flow support the creation of the novel aspects of the SoC design.
- Projects have a type, either active, complete (case study) or being formulated (request for collaboration)
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Sharing information on projects much earlier than traditional academic collaboration is encouraged. Historically knowledge sharing has been at the end of the research activity, with published papers and results. As well as write up of finished projects ("case study"), ongoing projects under development ("projects") there are projects that are still being formulated ("request for collaboration") listed. We want to encourage people to engage with the project teams, for example, adding a comment to a specific project page or joining a project.
Latest Reference Design Projects
David Flynn
The Arm Cortex-M55 AIoT SoC design platform is an AIoT subsystem that allows custom SoC designers to integrate their hardware circuits and embedded software for differentiation. The platform is developed by TSRI (Taiwan Semiconductor Research Institute) to support academic research on SoC design. It's built on the Arm Corstone-300 reference package, featuring the Cortex-M55 CPU and Ethos-U55 NPU.
CHI-SHI CHEN
On-chip SRAM in ASICs can use a significant area, which equates to a significant cost. One solution is to make the memory off-chip. This project explores the use of Arm IP to create an SRAM chiplet design. The benefit is that standard memory chiplets can be fabricated at lower cost and used across multiple projects, miminising silicon area to the unique project needs.
Daniel Newbrook
The aim of this project is to define a mixed signal subsystem for the nanosoc reference design.
The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system. In order to interface with real-world signals in a digital System on Chip ("SoC"), an analog to digital conversion ("ADC") is needed.
Latest Collaborative Projects
For the first tape out of nanosoc, the instruction memory was implemented using SRAM. Whilst this meant that the read bandwidth from this memory was very fast. It also meant that on a power-on-reset, all the code was erased as SRAM is volatile memory. An alternative use of non-volatile memory would benefit applications where deployment of the ASIC does not allow, or simply time is not available for programming the SRAM after every power up.
There has been much request within the SoC Labs community for an Arm A-Class SoC that can support a full operating system platform, undertake more complex compute tasks and enable more complicated software loads. The Cortex-A53 is Arm's most widely deployed 64-bit Armv8-A processor and can provide these capabilities with power efficiency
This project aims to design and implement a high capacity memory subsystem for Arm A series processor based SoC designs. The current focus of the project is the design and implementation of a Memory Controller for DDR4 memory.
Srimanth Tenneti
The Synopsys HAPS® System adds additional capabilities to the FPGA-based prototyping environments SoC Labs can use to support projects. The HAPS® system provides a greater amount of logic resources supporting development of larger SoC designs. It can be used to support multiple projects simultaneously. It is used by many semiconductor companies, including arm for their CPU verification. This collaboration project will use the HAPS® system in SoC Labs projects and share with the community experience in utilising such systems.
John Darlington
Latest Competition Projects
Project Overview:
Our innovative SoC design for precision agriculture revolutionizes field management by deploying a robust mesh network of sensor-based devices, capable of detailed monitoring and swift response to variations in soil health, erosion, drought, and pest activities. This system not only ensures reliability through its mesh architecture—eliminating single points of failure—but also incorporates diverse sensors for comprehensive data acquisition. It's engineered for energy efficiency to sustain operation throughout an entire crop season, significantly optimizing resource use and reducing waste.
This project focuses on developing a plant growth monitoring system for space exploration missions using the ARM Cortex-M0 microcontroller core. The projects aim to develop a SOC based on ARM M0 core for interactive plant monitoring by interfacing AHB lite, GPIO, timers, and communication protocols such as UART, I2C, SPI, and co-processors. This project also proposes two co-processors for interactive plant monitoring and control. One AI co-processor for classification and prediction of plant and environmental data.
Nowadays, rotating machine is the power source for most production equipment and is widely used in manufacturing factories. Common rotating machinery mainly includes bearings, gears, shafts, and the others. However, rotating machines suffer from frequent collisions and vibrations which lead to wearing and aging, which increases the chance of failure in the overall system operation. This make the cost of factories increase and the quality of production deteriorate. Therefore, the industries gradually value the usage of accurate and efficiency predictive maintenance system.
Latest Completed Project Milestones
| Project | Name | Target Date | Completed Date | Description | ||||||
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| Arm Cortex-A53 processor | FPGA SoC Prototyping design flows |
Prototype the CPU subsystem in FPGA |
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| Arm Cortex-A53 processor | Fix issues with QSPI |
Fix QSPI issues now that system successfully boots |
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| Arm Cortex-A53 processor | Minimum bootable system |
Build minimum capable system and boot compiled software. Including Cortex A53, SRAM, UART, and XiP QSPI |
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| Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference | Demo on SoCLabs test board |
Implementation of a demo displaying the classification of a subest of FashionMNIST test images using the Fast-kNN engine on the screen of the SoCLabs test board. Because of a conflict between accessing the micro-SD card contents and writing to the board's screen through the shared SPI bus, it is currently not possible to switch between loading data from the SD card and printing content to the display. Therefore, all the the data are preloaded from the micro-SD card to the RP2040, which restricted the number of train/test images to 160 and 27 respectively. |
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| Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference | Inference statistics capture |
Implementation of software tests on the SoCLabs demo board The aim of the software tests were to capture statistics about the average time required to run all the dot product calculations while running kNN inference for an unlabelled image. Carrying out the same computational load in software, without using the Fast-kNN engine was set as the comparison baseline.
The overall speedup observed was approximately a reduction in average compute time by x3000. However, the implementation of the computations in software could perhaps be implemented in a more efficient way, which could decrease the actual speedup obtained by Fast-kNN engine.
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| Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference | First abstract description of project goals |
Rough outline of the project's goals, hardware accelerator idea and motivation. |
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| SRAM Chiplet | Floor Planning |
Basic backend flow and floorplanning |
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| SRAM Chiplet | Logical verification |
Verification of the SRAM controller |
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| SRAM Chiplet | Architectural Design |
Design the basic architecture and build an initial wrapper for the SRAM chiplet |
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| Sensing for Precision Agriculture | Milestone #5: Initial SoC Internal Layout |
Using a block diagram (or something similar), to create plan for SoC internal modules, and how these will be connected together. Including modules for the ARM processor core, each sensor, and additional peripherals that may be required (such as memory and networking). Communication specifications between these modules should also be chosen at this stage (DMA, Bus/Interconnect, FIFO, etc.). 24/8/24: Used ARM DesignStart IP to start with a bare-bones system. |