Use the Tabs below to find information on community projects. Project pages have links to the 'technology' and 'design flow' stages used and ways you can comment on or join a project.
- Projects are key to community hardware design
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As a community hardware design activity we form our collaborations around shared design actions making Projects a core of the SoC Labs community. Projects help us share and reuse hardware and software developments around core Arm IP to help us in our research goals.
- A project, takes technology and uses a design flow to make a SoC.
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A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of a system. Any System On Chip usually involves the use of pre-existing IP blocks. A project team can select IP from the technology section of the site during the first stage of a design flow, Architectural Design. Later stages in the design flow support the creation of the novel aspects of the SoC design.
- Projects have a type, either active, complete (case study) or being formulated (request for collaboration)
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Sharing information on projects much earlier than traditional academic collaboration is encouraged. Historically knowledge sharing has been at the end of the research activity, with published papers and results. As well as write up of finished projects ("case study"), ongoing projects under development ("projects") there are projects that are still being formulated ("request for collaboration") listed. We want to encourage people to engage with the project teams, for example, adding a comment to a specific project page or joining a project.
Latest Reference Design Projects
The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC. This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.
Daniel Newbrook
David Flynn
Latest Collaborative Projects
Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. With NanoSoC, there are multiple options for performing system-level verification.
David Mapstone
Motivation
At SoC Labs, we have need of an accelerator to test our SoC infrastructure and confirmation of our accelerator wrapper design to get size and performance information as well as to try and get ahead and uncover potential problems researchers may experience trying to put their IP into the reference SoC.
Specification
The preliminary design has been broken into two main blocks:
Latest Competition Projects
Kun-Chih (Jimmy) Chen
Autonomous mobile robots (AMRs) have been proven useful for smart factories and have the potential to revolutionize critical missions, such as disaster rescue. AMRs can perceive the environment, plan for assigned tasks, and act on the plan. Motion control is critical to the robot's action, which is accomplished through trajectory optimization to refine the robot's states using a physics model. However, the high computational complexity of trajectory optimization poses significant challenges for AMRs with limited power and computing resources.
This project focuses on developing a plant growth monitoring system for space exploration missions using the ARM Cortex-M0 microcontroller core. The projects aim to develop a SOC based on ARM M0 core for interactive plant monitoring by interfacing AHB lite, GPIO, timers, and communication protocols such as UART, I2C, SPI, and co-processors. This project also proposes two co-processors for interactive plant monitoring and control. One AI co-processor for classification and prediction of plant and environmental data.
CMOS image sensors (CIS) play a crucial role in the imaging industry. CIS produces low-quality images in low-light conditions. Single Photon Avalanche Diode (SPAD) is a device used for low-light imaging because of its ability to detect single photons of light. To detect a single light photon, SPAD is biased above its breakdown voltage (Gieger mode). When the photon hits the active area during Geiger mode, a significant reverse current (avalanche current) is observed.
Latest Completed Project Milestones
| Project | Name | Target Date | Completed Date | Description |
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| Hell Fire SoC | Systolic Array Design |
We developed a Processing Element (PE) comprising an accumulator and a multiplier for the Systolic Array implementation within our SoC. To ensure the IP's readiness for successive cycles of operations and avoid a global reset, we adopted a separate reset mechanism for the accumulator. This approach enhances the efficiency of the Systolic Array, allowing for seamless and independent reset of individual PEs during each cycle of computation. The use of separate resets minimizes overhead and contributes to improved performance and scalability of the overall system. 
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| Hell Fire SoC | Accelerator IP Interface |
We opted for 32-bit wide Non-Sequential transfers to provide continuous data delivery to the Array Interface IP. This purposeful approach provides efficient data transmission while also simplifying the overall architecture. We achieve exact data transfer throughout the system by applying appropriate control signals. This method helps to a more streamlined and ordered data flow, which improves the functionality of the Array IP. The usage of 32-bit data width, together with diligent control signal management, ensures accurate and timely data transmission, eventually improving system performance. |
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| Hell Fire SoC | AHB Memory Interface Design |
This Interface implements a byte-addressable memory interface assuming a 32-bit memory width. |
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| Hell Fire SoC | AHB GPIO Interface |
AHB Based GPIO Interface |
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| Hell Fire SoC | Array Alignment Interface |
As the data to the array has to be aligned we plan to implement a data storage, alignment, and delivery architecture that accepts the data via the incoming AHB-Lite transfers and performs the operation and delivers the results back to the memory via the memory interface. 
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