Overview

The verification strategy for the SNN IP is divided into two primary phases:

1. Block-Level Interface Verification: Using Cocotb for agile and detailed functional verification of the AHB interface.
2. System-Level Integration Verification: Using the SoCLab socsim tool to validate the IP’s operation within a complete System-on-Chip (SoC) environment involving a DMA PL230 controller and software drivers.

Interface Verification with Cocotb

To ensure the SNN IP’s AHB interface strictly adheres to bus protocols, we employ a Cocotb-based co-simulation stack as illustrated in the architecture diagram:

• Python Testbench: High-level test cases are written in Python, allowing us to leverage powerful data manipulation libraries (e.g., NumPy) to generate test vectors and golden models for the SNN.
• Cocotb & VPI: The Cocotb framework manages the synchronization between the Python environment and the RTL simulator (QuestaSim) via the Verilog Procedural Interface (VPI).

• Verification Flow: We developed an AHB Master agent using cocotb in Python to drive transactions (reads/writes) to the SNN IP’s configuration registers. This phase ensures that the control logic and internal registers are correctly accessible.

  

   

Figure 1. Cocotb testbench architecture 

System-Level Simulation with socsim and DMA PL230

To verify the SNN IP’s performance and its interaction with other SoC components, we perform full-system simulation using the socsim tool provided by SoCLab.

• Hardware Configuration:  The simulation environment includes the SNN IP, the PL230 DMA Controller, and a processing subsystem. The DMA PL230 is responsible for high-speed data movement, offloading the CPU from manual data transfers.
• Software-Driven Verification:  We developed an embedded software program to handle the spike train preprocessing. This software converts raw neural data into a format compatible with the SNN IP's input buffer.
  • The software further configures the DMA PL230 descriptors to establish a communication link, enabling the automated transfer of the preprocessed spike trains from memory to the SNN IP.
• Objectives: This phase validates the data-path integrity, interrupt handling, and the timing synchronization between the software, the DMA, and the SNN IP.

Introduction

The simulation phase serves as the definitive validation of the integrated system. By following the strategy outlined in the Verification Methodology, we executed a full-system simulation to ensure that the SNN IP, the DMA PL230, and the CPU work in perfect synchrony. This simulation verifies the entire data path, from the initial storage of neural parameters in system memory to the final inference results generated by the SNN core.

System Simulation Execution Flow

The simulation mimics the real-world operational sequence of the SoC, divided into five critical stages:

• Stage 1: System Boot & Data Initialization Upon system reset, the simulation environment loads the preprocessed spike train and synaptic weights into the system RAM. This represents the "Golden Data" prepared by our software preprocessing scripts.
• Stage 2: Processor Configuration The CPU executes the initialization code, sending AHB write transactions to configure the control registers of both the DMA PL230 and the SNN IP. In this stage, parameters such as the number of neurons, thresholds, and transfer lengths are established.
• Stage 3: Weight Loading via DMA The DMA PL230 takes control of the bus to perform a high-speed burst transfer, moving the weight matrices from the system RAM directly into the internal SRAM of the SNN IP. This verifies the IP's ability to handle DMA-driven AHB slave writes.
• Stage 4: Spike Train Streaming Once the weights are loaded, the DMA initiates the transfer of the spike train into the IP's input buffer. This stage is critical for validating the synchronization between the producer (DMA) and the consumer (SNN IP).
• Stage 5: Neural Computation & Inference The SNN IP begins the spiking neural processing. The simulation tracks the membrane potential updates and spike generations across the programmed number of timesteps. Once the computation is complete, the IP signals the end of the task, and the results are read back for verification.

Figure 1. The configuration write transaction and weight transfer process

Figure 2. The spike train write transaction from RAM to buffer within SNN IP

Figure 3. an example result of SNN IP's operation

Introduction

The Register Transfer Level (RTL) generation phase is a critical step in transforming our architectural concepts into a verifiable digital system. For this project, we have developed a high-performance SNN IP by utilizing a modular design approach. By abstracting the hardware into functional blocks of registers and combinational logic, we ensure the design is both scalable and compatible with standard System-on-Chip (SoC) integration flows. Our RTL description serves as the foundation for synthesis, where the design is eventually mapped to physical logic gates.

SNN IP Architecture and Component Integration

The RTL of our SNN IP is composed of two primary sub-modules, representing a balance between custom high-performance logic and industry-standard connectivity:

• Custom SNPC Core (In-house RTL): The heart of the IP is the SNPC (Spiking Neural Processing Core). This block was developed in-house to implement the specific spiking neural network mathematics and neuron dynamics required for our application. The RTL defines the data flow between registers for membrane potential updates, thresholding logic, and spike generation.
• AHB Interface (nanoSoC Integration): To ensure seamless communication within a modern SoC environment, we integrated an AHB (Advanced High-performance Bus) interface sourced from the nanoSoC framework. Utilizing this pre-verified interface allows the SNN IP to function as a standard memory-mapped peripheral, enabling the CPU or DMA to configure registers and move spike data efficiently.

RTL Development Flow

The generation of the final RTL involves a multi-step integration process:

1. Module Interfacing: We developed a wrapper layer to bridge the SNPC core's internal signals to the AHB bus signals (HADDR, HWDATA, HRDATA, etc.). This ensures that the custom neural logic can be controlled via standard bus transactions.
2. Hierarchical Integration: The project RTL is organized into a clean directory structure that separates the core compute logic from the bus-level primitives. This modularity allows us to optimize the SNPC core independently of the interface logic.
3. Synchronization: Since the design is a synchronous digital system, all data transfers between the AHB registers and the SNN compute engine are carefully synchronized to the system clock, preventing metastability and ensuring data integrity during high-speed spike processing.