Use the Tabs below to find information on community projects. Project pages have links to the 'technology' and 'design flow' stages used and ways you can comment on or join a project.

Projects are key to community hardware design

As a community hardware design activity we form our collaborations around shared design actions making Projects a core of the SoC Labs community. Projects help us share and reuse hardware and software developments around core Arm IP to help us in our research goals.

A project, takes technology and uses a design flow to make a SoC.

A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of a system. Any System On Chip usually involves the use of pre-existing IP blocks. A project team can select IP from the technology section of the site during the first stage of a design flow, Architectural Design. Later stages in the design flow support the creation of the novel aspects of the SoC design.

Projects have a type, either active, complete (case study) or being formulated (request for collaboration)

Sharing information on projects much earlier than traditional academic collaboration is encouraged. Historically knowledge sharing has been at the end of the research activity, with published papers and results. As well as write up of finished projects ("case study"), ongoing projects under development ("projects") there are projects that are still being formulated ("request for collaboration") listed. We want to encourage people to engage with the project teams, for example, adding a comment to a specific project page or joining a project.

Latest Reference Design Projects

Reference Design
Active Project
soclabs nanosoc microcontroller framework - 2024
soclabs

nanosoc - baseline Cortex-M0 microcontroller SoC (2024 update)
A small SoC development framework to support easy integration and evaluation of academic developed research hardware such as a custom accelerators or signal processing sub-systems.
Reference Design
Active Project
TSRI Arm Cortex-M55 AIoT SoC Design Platform

TSRI Arm Cortex-M55 AIoT SoC Design Platform
 What is TSRI Arm Cortex-M55 AIoT SoC Design Platform?

The Arm Cortex-M55 AIoT SoC design platform is an AIoT subsystem that allows custom SoC designers to integrate their hardware circuits and embedded software for differentiation. The platform is developed by TSRI (Taiwan Semiconductor Research Institute) to support academic research on SoC design. It's built on the Arm Corstone-300 reference package, featuring the Cortex-M55 CPU and Ethos-U55 NPU.

Reference Design
Active Project
Imrpoved power domain structure for nanosoc
dwn @ soclabs

nanoSoC Low Power Implementation

As part of plans for continued development of nanoSoC one area that requires improvement is the power structure of system. The first iteration of nanoSoC contained 2 power domains: the accelerator domain and the remainder of the SoC. Both power domains were connected to external pins to allow connection to separate external voltage regulators and power measurement ICs, as implemented in the first version of the nanoSoC testboard.

Reference Design
Active Project
Block Diagram of SRAM chiplet

SRAM Chiplet

On-chip SRAM in ASICs can use a significant area, which equates to a significant cost. One solution is to make the memory off-chip. This project explores the use of Arm IP to create an SRAM chiplet design. The benefit  is that standard memory chiplets can be fabricated at lower cost and used across multiple projects, miminising silicon area to the unique project needs.

Latest Collaborative Projects

Collaborative
Active Project

Indonesia Collaborative SoC Platform

This program is dedicated to the development of a System on Chip (SoC) platform, specifically designed to support learning and research activities within Indonesian academic institutions. The platform serves as an educational and research tool for students, lecturers, and researchers to gain hands-on experience in digital chip design.

Collaborative
Active Project
AHB Qspi architectural design
dwn @ soclabs

AHB eXcecute in Place (XiP) QSPI

The instruction memory in the first tape out of nanosoc was implemented using SRAM. The benefit was the read bandwidth from this memory was very fast, the downside was on a power-on-reset, all the code was erased as SRAM is volatile memory. An alternative use of non-volatile memory would benefit applications where  deployment of the ASIC does not allow, or simply time is not available for programming the SRAM after every power up. 

Collaborative
Case Study
A53 simplified testbench
SoClabs

Arm Cortex-A53 processor

There is growing interest within the SoC Labs community for an Arm A-Class SoC that can support a full operating system, undertake more complex compute tasks and enable more complicated software directed research. The Cortex-A53 is Arm's most widely deployed 64-bit Armv8-A processor and can provide these capabilities with power efficiency. 

Collaborative
Request of Collaboration
High Capacity Memory Subsystem Development

This project aims to design and implement a high capacity memory subsystem for Arm A series processor based SoC designs.  The current focus of the project is the design and implementation of a Memory Controller for DDR4 memory. 

Latest Competition Projects

Competition 2025
Competition: Collaboration/Education

RF-Powered Sensor Platform for Intelligent Groceries Transportation Monitoring

This project aims to develop an advanced RF energy harvesting (EH) receiver chip specifically designed to power embedded sensors for monitoring the condition of groceries during transportation. The receiver chip captures wireless energy transmitted from phased array antennas and converts it into electrical power that is used to operate onboard sensors, which continuously monitor critical parameters such as temperature and humidity inside delivery trucks.

Competition 2025
Competition: Hardware Implementation

Neural Activity Processor

Stroke and epilepsy are among the most common debilitating neurological conditions, with a worldwide prevalence of 100 million people (World Stroke Organization, 2022) and 50 million people (World Health Organization, 2024), respectively. Present-day approaches for treating neurological and neurosurgical conditions include physiotherapy, pharmacological treatment, surgical excision, and interventions such as deep brain stimulation.

Competition 2025
Competition: Collaboration/Education
An Efficient Hardware-based Spike Train Repetition for Energy-constrained Spiking Neural Networks

Spiking Neural Networks (SNNs) require processing a large number of spikes to achieve high classification accuracy. However, this results in frequent memory accesses to fetch synaptic weights, which significantly increases energy dissipation in SNN systems. To address this challenge, we propose a unique technique called the Repetitive Spike Train (RST) method. By exploiting the temporal similarity of spike trains across time steps, RST minimizes redundant spike train updates and reduces memory read/write operations.

Competition 2025
Competition: Hardware Implementation
Aspen annotated die photo

Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads

Aspen is a unified accelerator for deep neural network (DNN)-based extended reality perception workloads. Aspen proposes a mixed-precision quantization scheme using the posit datatype to reduce memory usage while maintaining accuracy, a DNN accelerator for mixed-precision posit datatypes, and efficient data prefetching and data layout to minimize data reorganization. The Aspen system-on-chip has an Arm Cortex-M3 CPU, a mixed-precision posit-based DNN accelerator, and 4 megabytes of SRAM partitioned into eight 512 KB banks, connected through a 128-bit-wide interconnect.

Latest Completed Project Milestones

Project Name Target Date Completed Date Description
PCK600 Integration in megaSoC Getting Started

Decide on the project goal

PCK600 Integration in megaSoC IP Selection

Chose IP relevant for this design

PCK600 Integration in megaSoC Architectural Design
Neural Activity Processor Getting Started
Sensing for Precision Agriculture Simulation

Simulation of an integration test of our custom RTL working with NanoSoC.

Completed 5th April 2025.

Sensing for Precision Agriculture Getting Started
  • Investigate and decide on the necessary peripherals such as ADC, RTC, Timers, PMICs, GPS modules, I2C, SPI, and communication modules. Done.
  • Define the memory requirements for the SoC and create an address map to interface with each peripheral, ensuring proper allocation and management. Done.
  • Move away from the Design Start Kit and migrate to NanoSoC with AAA IP Done.
  • Project Management:
    • Get TSMC PDK access through Europractice via S3B (Government). Moved to "Technology Selection" milestone.
    • Get Cadence license through existing university contacts. Done.
Sensing for Precision Agriculture Generate RTL

Milestone #6: APB Wrapper

  • Create APB Wrapper for our IP (to interface the Cortex M0 with analog mux, ADC, FIFO queue, etc).
  • Document on the SoCLabs page.
  • Create unit tests including C code to test APB register access.
Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads Getting Started
Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads IP Selection
Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads Technology Selection

Latest Project Updates