Use the Tabs below to find information on community projects. Project pages have links to the 'technology' and 'design flow' stages used and ways you can comment on or join a project.
- Projects are key to community hardware design
-
As a community hardware design activity we form our collaborations around shared design actions making Projects a core of the SoC Labs community. Projects help us share and reuse hardware and software developments around core Arm IP to help us in our research goals.
- A project, takes technology and uses a design flow to make a SoC.
-
A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of a system. Any System On Chip usually involves the use of pre-existing IP blocks. A project team can select IP from the technology section of the site during the first stage of a design flow, Architectural Design. Later stages in the design flow support the creation of the novel aspects of the SoC design.
- Projects have a type, either active, complete (case study) or being formulated (request for collaboration)
-
Sharing information on projects much earlier than traditional academic collaboration is encouraged. Historically knowledge sharing has been at the end of the research activity, with published papers and results. As well as write up of finished projects ("case study"), ongoing projects under development ("projects") there are projects that are still being formulated ("request for collaboration") listed. We want to encourage people to engage with the project teams, for example, adding a comment to a specific project page or joining a project.
Latest Reference Design Projects
The aim of this project is to define a mixed signal subsystem for the nanosoc reference design.
In order to interface with real-world signals in a digital SoC, an analog to digital conversion is needed. The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system.
Daniel Newbrook
A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board provides a complete test environment for ASIC designs based on the nanoSoC reference design and enables the showcase of any custom designs that utilise it. Reviewing the function of nanoSoC identifies a number of design criteria for the test board:
The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC. This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.
Latest Collaborative Projects
The Arm PL022 provides an interface for synchronous serial communication with peripheral devices connected to the SoC via the Advanced Peripheral Bus (APB). It supports a choice of interface operation, Motorola compatible Serial Peripheral Interface (SPI), National Semiconductor Microwire, or Texas Instruments synchronous serial interface. See the Techology page for details.
To design and verify a simple PLL for use as generator of clock signals in System on Chip design. The desired outcome from this project should be the following:
Clock generation for frequencies between 60 MHz and 1.2 GHzInclude PLL-lock signal for system start upLow clock uncertainty below 5% (transition time and jitter)Integer clock divider which can be updated at run timeMinimal areaThe resulting IP for these component blocks will be made available to the soclabs community for the upcoming design contest.
Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. With NanoSoC, there are multiple options for performing system-level verification.
David Mapstone
David Flynn
Latest Competition Projects
Our innovative SoC design for precision agriculture revolutionizes field management by deploying a robust mesh network of sensor-based devices, capable of detailed monitoring and swift response to variations in soil health, erosion, drought, and pest activities. This system not only ensures reliability through its mesh architecture—eliminating single points of failure—but also incorporates diverse sensors for comprehensive data acquisition. It's engineered for energy efficiency to sustain operation throughout an entire crop season, significantly optimizing resource use and reducing waste.
This project focuses on developing a plant growth monitoring system for space exploration missions using the ARM Cortex-M0 microcontroller core. The projects aim to develop a SOC based on ARM M0 core for interactive plant monitoring by interfacing AHB lite, GPIO, timers, and communication protocols such as UART, I2C, SPI, and co-processors. This project also proposes two co-processors for interactive plant monitoring and control. One AI co-processor for classification and prediction of plant and environmental data.
Nowadays, rotating machine is the power source for most production equipment and is widely used in manufacturing factories. Common rotating machinery mainly includes bearings, gears, shafts, and the others. However, rotating machines suffer from frequent collisions and vibrations which lead to wearing and aging, which increases the chance of failure in the overall system operation. This make the cost of factories increase and the quality of production deteriorate. Therefore, the industries gradually value the usage of accurate and efficiency predictive maintenance system.
This Project is to develop traffic light system that can reduce traffic congestion with the aid of counters for each lane and acts wisely with the intersection in real time based with a fixed time constrain, include both hardware and software requirements using SOC FPGA technology with fundamental specification for the Register Transfer Level (RTL).
AFOLAYAN, ABDULSAMAD
Latest Completed Project Milestones
| Project | Name | Target Date | Completed Date | Description |
|---|---|---|---|---|
| Test draft | Synthesis |
Just testing preview |
||
| ARM Cortex M0 Based SoC for Biomedical Applications | FPGA Prototyping |
|
||
| Sensing for Precision Agriculture | Milestone #3: Determine required processor and peripheral features for precision agriculture application. |
|
||
| Battery Management System-on-chip (BMSoC) for large scale battery energy storage | Architectural Design |
|
||
| Battery Management System-on-chip (BMSoC) for large scale battery energy storage | Logical Design |
Domain Specific Design
|
||
| Sensing for Precision Agriculture | Milestone #2: Learning SoC design basics |
2. Reviewing NanoSoC:
Completed: Team successfully up to date. |
||
| Sensing for Precision Agriculture | Milestone #1: Determine project scope and focus. |
|
||
| ARM Cortex M0 Based SoC for Biomedical Applications | Architectural Design |
In this milestone, we aim to define the hardware used in the SoC. Behavioural level code has been written in Verilog to allow protocol conversion between AHB Lite protocol used in ARM Cortex M0 and UART/I2C peripheral. |
||
| ARM Cortex M0 Based SoC for Biomedical Applications | Architectural Design |
After defining the customized hardware for the UART and I2C interfaces, we develop customized software. This will help the user and programmers to work with the SoC without worrying about the underlying hardware. |
||
| Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks | Arm Cortex A53 Configuring and Synthesis |
|