Use the Tabs below to find information on community projects. Project pages have links to the 'technology' and 'design flow' stages used and ways you can comment on or join a project.

Projects are key to community hardware design

As a community hardware design activity we form our collaborations around shared design actions making Projects a core of the SoC Labs community. Projects help us share and reuse hardware and software developments around core Arm IP to help us in our research goals.

A project, takes technology and uses a design flow to make a SoC.

A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of a system. Any System On Chip usually involves the use of pre-existing IP blocks. A project team can select IP from the technology section of the site during the first stage of a design flow, Architectural Design. Later stages in the design flow support the creation of the novel aspects of the SoC design.

Projects have a type, either active, complete (case study) or being formulated (request for collaboration)

Sharing information on projects much earlier than traditional academic collaboration is encouraged. Historically knowledge sharing has been at the end of the research activity, with published papers and results. As well as write up of finished projects ("case study"), ongoing projects under development ("projects") there are projects that are still being formulated ("request for collaboration") listed. We want to encourage people to engage with the project teams, for example, adding a comment to a specific project page or joining a project.

Latest Reference Design Projects

Reference Design
Active Project
Block Diagram of SRAM chiplet

SRAM Chiplet

On-chip SRAM in ASICs can use a significant area, which equates to a significant cost. One solution is to make the memory off-chip. This project explores the use of Arm IP to create an SRAM chiplet design. The benefit  is that standard memory chiplets can be fabricated at lower cost and used across multiple projects, miminising silicon area to the unique project needs.

Reference Design
Active Project
Nanosoc ADC Integration
SoClabs

ADC Integration in nanoSoC
Rationale

The aim of this project is to define a mixed signal subsystem for the nanosoc reference design. 

In order to interface with real-world signals in a digital SoC, an analog to digital conversion is needed. The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system. 

Reference Design
Active Project
High bandwidth expansion subsystem block diagram
SoClabs

High Bandwidth Expansion Subsystem
The high bandwidth expansion subsystem is for use in systems where high bandwidth transfer to the hardware accelerator is required. This subsystem can be added to a larger SoC through the 2x full AXI ports (1 subordinate and 1 manager).
Reference Design
Active Project
Testboard and nanosoc Chip
SoClabs

nanoSoC Test/development Board

A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board provides a complete test environment for ASIC designs based on the nanoSoC reference design and enables the showcase of any custom designs that utilise it.  Reviewing the function of nanoSoC identifies a number of design criteria for the test board:

Latest Collaborative Projects

Collaborative
Request of Collaboration
©2024 Synopsys, Inc. All rights reserved.

Use of the Synopsys HAPS® FPGA-based prototyping environment

The Synopsys HAPS® System adds additional capabilities to the FPGA-based prototyping environments SoC Labs can use to support projects. The HAPS® system provides a greater amount of logic resources supporting development of larger SoC designs. It can be used to support multiple projects simultaneously. It is used by many semiconductor companies, including arm for their CPU verification. This collaboration project will use the HAPS® system in SoC Labs projects and share with the community experience in utilising such systems.

Collaborative
Active Project
In partnership with Canada
vecteezy.com/Free License

Geographical support for Canada

This collaboration project is aimed at providing specific tailored activities to the local geography in Canada by developing local actions that will help stimulate academics and their institutions and the broader semiconductor industry supporters to create new and exciting SoC design projects. 

It may include holding specific local physical meetups where people can exchange design ideas.

It may include utilising locally provided routes to fabrication.

It may include sharing hard to locate test capability across academic institutions.

Collaborative
Request of Collaboration

Interfacing with the Arm PL022 within a cocotb testbench

The Arm PL022 provides an interface for synchronous serial communication with peripheral devices connected to the  SoC via the Advanced Peripheral Bus (APB). It supports a choice of interface operation, Motorola compatible Serial Peripheral Interface (SPI), National Semiconductor Microwire, or Texas Instruments synchronous serial interface. See the Techology page for details. 

Collaborative
Request of Collaboration

Basic PLL with TSMC 65nm

To design and verify a simple PLL for use as generator of clock signals in System on Chip design. The desired outcome from this project should be the following:

Clock generation for frequencies between 60 MHz and 1.2 GHzInclude PLL-lock signal for system start upLow clock uncertainty below 5% (transition time and jitter)Integer clock divider which can be updated at run timeMinimal area

The resulting IP for these component blocks will be made available to the soclabs community for the upcoming design contest.

Latest Competition Projects

Competition 2024
Competition: Hardware Implementation
Accelerated Tiny-Transformer IP

FPGA-Powered Acceleration for NLP Tasks

Project Overview:

Competition 2024
Competition: Hardware Implementation

Sensing for Precision Agriculture

Our innovative SoC design for precision agriculture revolutionizes field management by deploying a robust mesh network of sensor-based devices, capable of detailed monitoring and swift response to variations in soil health, erosion, drought, and pest activities. This system not only ensures reliability through its mesh architecture—eliminating single points of failure—but also incorporates diverse sensors for comprehensive data acquisition. It's engineered for energy efficiency to sustain operation throughout an entire crop season, significantly optimizing resource use and reducing waste.

Competition 2024
Competition: Hardware Implementation
Monitoring and enhancing plant growth in space ecosystems

This project focuses on developing a plant growth monitoring system for space exploration missions using the ARM Cortex-M0 microcontroller core. The projects aim to develop a SOC based on ARM M0 core for interactive plant monitoring by interfacing AHB lite, GPIO, timers, and communication protocols such as UART, I2C, SPI, and co-processors.  This project also proposes two co-processors for interactive plant monitoring and control. One AI co-processor for classification and prediction of plant and environmental data.

Competition 2024
Competition: Hardware Implementation
Smart Machine Box for Industrial IoT with High Performance ASIC Prototyping System

Nowadays, rotating machine is the power source for most production equipment and is widely used in manufacturing factories. Common rotating machinery mainly includes bearings, gears, shafts, and the others. However, rotating machines suffer from frequent collisions and vibrations which lead to wearing and aging, which increases the chance of failure in the overall system operation. This make the cost of factories increase and the quality of production deteriorate. Therefore, the industries gradually value the usage of accurate and efficiency predictive maintenance system.

Latest Completed Project Milestones

Project Name Target Date Completed Date Description
SRAM Chiplet Floor Planning

Basic backend flow and floorplanning

SRAM Chiplet Architectural Design

Design the basic architecture and build an initial wrapper for the SRAM chiplet

SRAM Chiplet Logical verification

Verification of the SRAM controller 

Sensing for Precision Agriculture Milestone #4: Requirements for mixed signal, communication and processor components.

Mixed Signal 

  • Create list of the required sensors (electrochemical, optical, mechanical, dielectric, temperature) for soil monitoring application and examples of useful sensors available on the market. List all requirements for front-end conditioning of each type of measurement (e.g. precision required, how often each measurement is required and elements of analog circuitry like amplification stages). 

Communication (Networking) 

  • Determine the approach and scope of operation. Discuss and outline the set limits in terms of distance and frequency. Create a sets of block diagram to begin the approach to creating a basic outline. To be discussed with Analog front end team and processor team. Source a minimum of 4 research materials to reference a quick approach. 

Update (7/8/24): Listed requirements for electrochemical and temperature. Optical and mechanical have been discontinued due to practicality concerns. Still looking into dielectric sensing and networking.

Update (24/8/24): Networking is on hold for now. Started work on mixed signal sensor components.

Sensing for Precision Agriculture Milestone #5: Initial SoC Internal Layout

Using a block diagram (or something similar), to create plan for SoC internal modules, and how these will be connected together. Including modules for the ARM processor core, each sensor, and additional peripherals that may be required (such as memory and networking).

Communication specifications between these modules should also be chosen at this stage (DMA, Bus/Interconnect, FIFO, etc.).

24/8/24: Used ARM DesignStart IP to start with a bare-bones system.

Battery Management System-on-chip (BMSoC) for large scale battery energy storage Generate RTL
  • RTL design and behavioural simulation of the battery state monitoring methodology.
  • Synthesis and FPGA implementation of Hardware software codesign on Zedboard (Zynq-7000 SoC).

 

 

 

FPGA-Powered Acceleration for NLP Tasks Accelerator Design Flow

implemented encoder block with hardware utilization as 22 % LUTS and 7 % BRAM.

ip
FPGA-Powered Acceleration for NLP Tasks Behavioural Design

Implementation Phase:

  • Complete HLS of Tiny Transformer block components of input embedding.
  • Develop communication protocols between PS and PL parts of the SoC.
FPGA-Powered Acceleration for NLP Tasks Architectural Design

Project Kickoff:

  • Define project objectives and scope.
  • Review existing technologies and research relevant to Tiny Transformers and ARM Cortex integration.
FPGA-Powered Acceleration for NLP Tasks Behavioural Design

System Architecture Development:

  • Implement attention block and normalization block.