Use the Tabs below to find information on community projects. Project pages have links to the 'technology' and 'design flow' stages used and ways you can comment on or join a project.

Projects are key to community hardware design

As a community hardware design activity we form our collaborations around shared design actions making Projects a core of the SoC Labs community. Projects help us share and reuse hardware and software developments around core Arm IP to help us in our research goals.

A project, takes technology and uses a design flow to make a SoC.

A project has a timeframe and uses the two other significant aspects of a SoC development, the selection of technology or IP blocks that make up the SoC and the design flow that is followed from specification through to final instantiation of a system. Any System On Chip usually involves the use of pre-existing IP blocks. A project team can select IP from the technology section of the site during the first stage of a design flow, Architectural Design. Later stages in the design flow support the creation of the novel aspects of the SoC design.

Projects have a type, either active, complete (case study) or being formulated (request for collaboration)

Sharing information on projects much earlier than traditional academic collaboration is encouraged. Historically knowledge sharing has been at the end of the research activity, with published papers and results. As well as write up of finished projects ("case study"), ongoing projects under development ("projects") there are projects that are still being formulated ("request for collaboration") listed. We want to encourage people to engage with the project teams, for example, adding a comment to a specific project page or joining a project.

Latest Reference Design Projects

Reference Design
Active Project
Nanosoc ADC Integration

ADC Integration in nanoSoC

The aim of this project is to define a mixed signal subsystem for the nanosoc reference design. 

In order to interface with real-world signals in a digital SoC, an analog to digital conversion is needed. The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system. 

Reference Design
Active Project
High bandwidth expansion subsystem block diagram

High Bandwidth Expansion Subsystem
The high bandwidth expansion subsystem is for use in systems where high bandwidth transfer to the hardware accelerator is required. This subsystem can be added to a larger SoC through the 2x full AXI ports (1 subordinate and 1 manager).
Reference Design
Active Project
3D Render of nanoSoC test board

nanoSoC Test/development Board

A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board needs to provide a complete test environment for ASIC designs based on the nanoSoC reference design and enable showcase of any custom designs that utilise it. Reviewing the function of nanoSoC identifies a number of design criteria for the test board:

Serial Wire Debug (SWD) and UART debugger interfaceGPIO driver interface including data transportPower supply and monitoringClock and reset control

Based on these requirements, the following test board is under development:

Reference Design
Active Project

DMA 350 integration with nanoSoC

The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC.  This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.

Latest Collaborative Projects

Request of Collaboration

Interfacing with the Arm PL022 within a cocotb testbench

The Arm PL022 provides an interface for synchronous serial communication with peripheral devices connected to the  SoC via the Advanced Peripheral Bus (APB). It supports a choice of interface operation, Motorola compatible Serial Peripheral Interface (SPI), National Semiconductor Microwire, or Texas Instruments synchronous serial interface. See the Techology page for details. 

Request of Collaboration

Basic PLL with TSMC 65nm

To design and verify a simple PLL for use as generator of clock signals in System on Chip design. The desired outcome from this project should be the following:

Clock generation for frequencies between 60 MHz and 1.2 GHzInclude PLL-lock signal for system start upLow clock uncertainty below 5% (transition time and jitter)Integer clock divider which can be updated at run timeMinimal area

The resulting IP for these component blocks will be made available to the soclabs community for the upcoming design contest.

Active Project

System Verification of NanoSoC

Performing system-level verification on a System-on-Chip (SoC) design is crucial for ensuring the correct function and overall performance of the entire system, rather than individual components. With NanoSoC, there are multiple options for performing system-level verification.

Case Study

Building system-optimised AMBA interconnect
Example case-study of using the Arm CMSDK AMBA-AHB Bus-Matrix tools to build system-optimised interconnect.

Latest Competition Projects

Competition 2024
Competition: Hardware Implementation
Monitoring and enhancing plant growth in space ecosystems

This project focuses on developing a plant growth monitoring system for space exploration missions using the ARM Cortex-M0 microcontroller core. The projects aim to develop a SOC based on ARM M0 core for interactive plant monitoring by interfacing AHB lite, GPIO, timers, and communication protocols such as UART, I2C, SPI, and co-processors.  This project also proposes two co-processors for interactive plant monitoring and control. One AI co-processor for classification and prediction of plant and environmental data.

Competition 2024
Competition: Hardware Implementation
Smart Machine Box for Industrial IoT with High Performance ASIC Prototyping System

Nowadays, rotating machine is the power source for most production equipment and is widely used in manufacturing factories. Common rotating machinery mainly includes bearings, gears, shafts, and the others. However, rotating machines suffer from frequent collisions and vibrations which lead to wearing and aging, which increases the chance of failure in the overall system operation. This make the cost of factories increase and the quality of production deteriorate. Therefore, the industries gradually value the usage of accurate and efficiency predictive maintenance system.

Competition 2024
Competition: Collaboration/Education


This Project is to develop traffic light system that can reduce traffic congestion with the aid of counters for each lane and acts wisely with the intersection in real time based with a fixed time constrain, include both hardware and software requirements using SOC FPGA technology with fundamental specification for the Register Transfer Level (RTL).

Competition 2024
Competition: Hardware Implementation

ARM Cortex M0 Based SoC for Biomedical Applications

Conventional healthcare is expensive and reliant on the physical presence of the patients. Continuous health monitoring tracks vital health parameters like heart rate, blood pressure, etc. While these work well in measuring the parameters, modern-day devices rely on the cloud to compute and interpret data. This results in an increase in data transfer between the device and the cloud, and if this connection breaks, there can be no interpretation of data. Hence, there is a need to shift the computation to the hardware, referred to as "Edge Computing".

Latest Completed Project Milestones

Project Name Target Date Completed Date Description
Real-Time Edge AI SoC: High-Speed Low Complexity Reconfigurable-Scalable Architecture for Deep Neural Networks Arm Cortex A53 Configuring and Synthesis
  • ASIC synthesis of standalone Arm Cortex A53 is completed.
  • Area estimates has been reported as 4.9 sq. mm without using Tech Dependent cells.
Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Initial RTL Implementation

Familirisation with SoCLabs Accelerator Wrapper IP 

Implementation of Packet constructor wrapper for writing 128-bit dat packets to the device

Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Clock Tree Synthesis

Clock tree synthesis and timing optimisation

Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Tape Out

Submit for tapeout to europractice TSMC 65nm mini ASIC shuttle

Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Synthesis

Run synthesis and formal equivalence checks

Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Timing closure
Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Floor Planning
Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference DRC

Check DRC and fix any errors

Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference Final RTL submission

Submit the final design, integrated with nanoSoC for backend flow

Basic PLL with TSMC 65nm Basic System test and integration

Design and simulate the basic components of the PLL and test the full subsystem together