A System on Chip (SoC) usually has many functional blocks to deal with communication either on chip or the the external environment. For on chip communication the Advanced Microcontroller Bus Architecture is a common bus architecture.

Any System On Chip requires a bus mechanism to allow functional parts to exchange data. The ARM Advanced Microcontroller Bus Architecture is an open-standard, royalty-free, platform-independent, architecture for the connection and management of functional blocks in System On Chip design.

CoreLink NIC-400 can be used to create the Advanced Microcontroller Bus Architecture compliant Interconnect communication path between the functional blocks of the System on Chip.

The CoreLink NIC-450 provides additional Arm blocks to extend the NIC-400 capabilities:

QoS-400 Network Interconnect Advanced Quality of Service provides regulation of read and write request to manage traffic for specific latency applications.

The Arm CoreLink CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs. It enables big.LITTLE processing and I/O coherency for devices such as the Mali-T600 series GPU, and I/O masters like modem and USB.

CCI-500 Cache Coherent Interconnect provides high bandwidth access between CPUs and other SoC blocks including shared main memory and enables use of Arm big.LITTLE processing techniques between multiple cores. It supports up to four ACE masters, Arm processors, six ACE-Lite masters, eg.

CCI-550 provides high bandwidth access between CPUs and other SoC blocks including shared main memory supporting Arm big.LITTLE processing techniques with up to seven ACE/ACE-Lite masters ACE (max 6) for Arm processors, ACE-Lite (max 6) Mali GPU, etc.

ADB-400 AMBA Domain Bridge can form an asynchronous bridge between two components either as a Dynamic Voltage Frequency Scaling (DVFS) bridge with slave and master domains in different voltage domains or a clock bridge in the same voltage domain.

The XHB-400 has  an AXI4 slave and  AHB-Lite master interfaces and converts AXI4 to the AHB-Lite protocol with configurable data widths and zero latency conversion.

Offering a direct interface to the user through smartphones, Bluetooth and Bluetooth Low Energy (BLE) operate at 2.4 GHz and support a variety of network architectures including mesh networks, beacons, as well as point-to-point links.

Near Field Communication (NFC) relies on near-field electromagnetic coupling to securely transmit information wirelessly between compatible devices. NFC is widely used in authentication with NFC hardware becoming part of most smartphones.

High-Frequency (HF) and Ultra High-Frequency (UHF) radio frequency identification (RFID) are becoming pervasive technologies in retail and industrial applications.

Widely used in enabling wireless internet connectivity at high data rates, Wi-Fi mostly operates in the 2.4 GHz band alongside Bluetooth and other IEEE 802.15 standards and is based on the IEEE 802.11 standard.

The Arm Cortex-A series is a class of application processors that implement a Virtual Memory System Architecture (VMSA) that enable Operating Systems such as Linux to support the operation of multiple software applications.

The Cortex-A53 processor has an 8-stage, symmetric dual-issue in-order pipeline implementing the 64-bit Armv8-A architecture with one to four cores with automatic data cache coherency, the shared Level 2 cache can be up to 2MB, 128 bit ACE or CHI coherent system bus interface.

The Cortex-A35 processor is Arm’s most power-efficient application processor capable of seamlessly supporting 32-bit and 64-bit code. Supports one to four cores with automatic data cache coherency, a shared Level 2 cache, 128 bit ACE, CHI or AXI system bus interface. 

The Cortex-A34 processor has an 8-stage, in-order pipeline implementing the 64-bit Armv8-A architecture with one to four cores with automatic data cache coherency, a shared Level 2 cache, 128 bit ACE, CHI or AXI system bus interface. It has hardware virtualization support.

The Cortex-A32 processor has an 8-stage, in-order pipeline implementing the 32-bit Armv8-A architecture with one to four cores with automatic data cache coherency, a shared Level 2 cache, 128 bit ACE, CHI or AXI system bus interface improving efficiency over Cortex A7 and A5.

The Cortex-A7 processor builds on the energy-efficient 8-stage in-order pipeline of the Cortex-A5 processor, adding up to 1 MB Level 2 cache, 40 bit physical addressing to support Large Physical Address Extensions (LPAE), 64-bit load-store and 128-bit AMBA ACE bus. The Cortex-A7 processor provide

The Cortex-A5 processor (UP uniprocessor or MP multiprocessor) has an 8-stage in-order pipeline with dynamic branch prediction, 32 bit physical addressing, Level 1 cache, 64-bit AXI master interface and optionally either a Floating-Point Unit or a NEON Media Processing Engine.

The Cortex-M processors are aimed at microcontroller and embedded applications with a 32-bit architecture (Armv7-M supports the Thumb and Armv8-M a variant of the Thumb 32 instruction set), a Protected Memory System Architecture (PMSA) and run dedicated operating systems.

The Cortex-M55 implements the Arm v8.1-M Mainline architecture with a four stage in-order integer pipeline and M-profile Vector Extension (MVE) benefitting machine learning and signal processing applications.

The Cortex-M33 implements the ARMv8-M architecture with a three stage in-order pipeline supporting Thumb-1 and Thumb-2, single precision Floating Point Unit, Digital Signal Processing (DSP), saturated and Custom Instructions for external co-processor accelerators.

The Cortex-M23 implements the ARMv8-M architecture with a two-stage in-order pipeline supporting Thumb-1 and subset of Thumb-2 instructions with hardware multiply and divide in a low gate count similar to M0 and aimed at energy efficient embedded applications.

The Cortex-M7 implements the ARMv7E-M architecture using a 6 stage superscalar pipeline with branch prediction, instruction and data caches (64 bit buses) and tightly coupled memories (TCMs) to give nearly double the performance of M4 processor.

The Cortex-M4 implements the ARMv7-M architecture adding IEEE 754 compliant single precision Floating Point Unit and a range of saturating and SIMD instructions for Digital Signal Processing (DSP).

The Cortex-M3 implements the ARMv7-M architecture supporting Thumb-1 and Thumb-2 instructions with a 3-stage in-order pipeline, with hardware Divide and Multiply, and an additional nonprivileged mode (User Thread). It supports Bit-banding in the lowest 1MB of the SRAM and Peripheral memory allowi

The Cortex-M0+ implements the ARMv6-M architecture with a two-stage in-order pipeline and additonal clock gating to improve efficiency and a Memory Protection Unit supporting 8 protection regions to separate processes and privileges in the same gate count as MO.

The Cortex-M0 is a 32 bit processor is targeted at SoCs that require a low gate count (12-25k gates), small die area, high energy efficiency (0.012 mW/MHz Min Power with 50 MHz Max Freq) and is intended for microcontroller and embedded applications.

The Cortex-R Series is aimed at embedded Systems for precisely defined applications with either deterministic real time performance or  safety critical demands.

The Cortex-R52 processor implements the ARMv8-R architecture allowing support for a hypervisor and hosting multiple operating systems. Allows up to four processing units (quad-core) / 8 logical cores in Dual Core Lock Step (DCLS) using redundant cores in lockstep for fault detection.

The Cortex-R8 processor implements the ARMv7-R architecture. Allows up to four processing units (quad-core) running independently, each executing its own program with its own bus interfaces (Asymetric) or with a single operating system managing all cores (Symertric).

The Cortex-R5 processor implements the ARMv7-R architecture.

Mali Graphics Processor Unit (GPU) use 16x16 pixel tile-based rendering to minimize external memory accesses keeping the entire working set for a tile in fast on-chip memory tightly coupled to the shader core. Processing takes two passes, the first executes all the geometry processing and generat

Ethos-U55 is a micro Neural Processing Unit coprocessor to accelerate machine learning inference with a 

The G52 implements the Bifrost architecture supporting OpenGL 2.0 and Vulkan and Machine Learning (ML) and Augmented Reality (AR) with support for 8 bit dot product operations.

In order for an accelerator to be integrated within a SoC, the accelerator needs to share interfaces with the system. The natural interface exposed by an accelerator engine may be different from that accepted by the broader SoC.  In the case of the reference

The G31 implements the Bifrost architecture supporting OpenGL 2.0 and Vulkan with a simple 1 uni-pixel or dual-pixel shader core operating with a 650 MHz clock, small 4k load/store cache and optimised work registers for low energy and small area.

RenderScript is a language and API in Android OS that enables you to use different processors for compute intensive tasks.

RenderScript applications can be written to make optimal use of the GPU acceleration capabilities offered by the Mali RenderScript GPU accelerator

A Generic Interrupt Controller  providing registers for managing interrupt sources, interrupt behavior, and interrupt routing for up to 128 Armv8.0 A class processor cores such as the A53. It implements version 3.0 of the ARM Generic Interrupt Controller Architecture Specification. 

A Generic Interrupt Controller providing registers for managing interrupts for up to eight Armv7 A class processor cores such as the A7.

The PL192 VIC moves interrupt control to the AMBA AHB bus to manage service interrupt requests throughout a SoC.

The TZC-400 TrustZone Address Space Controller (TZC-400) implements filters between ACE-Lite masters and ACE-Lite slaves to perform security checks on transactions to memory or peripherals using up to eight separate regions in the address space, each with an individual security level setting. Eac

The Level 2 Cache Controller L2C-310 improves memory access speed within a SoC by implementing Level 2 memory caching (access within 8 cycles) using slave and master AMBA AXI interfaces, between Level 1 instruction and data caches (1-2 cycles) and  Level 3 main memory (30-100 cycles).

The MMU-500 System Memory Management Unit provides address and memory attribute translation from Virtual Memory spaces to the Physical Memory within the System on Chip. An SMMU is placed between a device and the system interconnect to translate addresses for Direct Memory Access requests for the

The BP140 AXI Memory Interface provides a single-port memory interface configurable for synchronous SRAM or ROM. It supports all AMBA AXI channels except the low power channel as it does not have a low-power mode of operation. It can be configured with data width of 64 bits or 32 bits.

The BP141 TrustZone Memory Adapter (TZMA) is an AMBA compliant System-on-Chip peripheral that enables a single physical memory cell of up to 2MB to be shared between a secure and a non-secure partition. It is compatible with the AXI internal memory interface (BP140).

A SoC requires multiple clock and power domains to be efficient. PCK-600 provides components to allow power control infrastructure to be distributed in a SoC in accordance with the Arm Power Control System Architecture using Q-Channel and P-Channel low power interfaces.

System-on-Chip (SoC) security depends on architectural and secure IP blocks in order to protect systems, networks, and data from a range of attacks and limit potential vulnerabilities.

The use of a Physically Unclonable Function (PUF) for key generation or encryption operations relies on process variation that are intrinsic in the manufacture of devices. In this example a Ring oscillator based PUF is implement.

The Arm True Random Number Generator is a component that generates standards compliant random bit streams.  It is designed for simple SoC integration connecting via an AMBA APB2 slave interface to the SoC system bus.

Corstone Subsystems combines the various system IP components for a specific processor and Arm architecture to simplify System on Chip designs. The contain reference designs that utilise the IP blocks to reduce design and verification effort.

Corstone-101 combines various system IP components for Cortex M3 based System on Chip designs and a subsystem (SSE-050) integrating the processor, memory, debug, security, and power control. It also contains the Cortex-M System Design Kit for SoC designs using the M0, M0+, M3 and m4 processors.

Corstone-201 combines various system IP components for Cortex M based System on Chip designs and a subsystem integrating the processor, memory, debug, security, and power control.

Corstone-102 combines various system IP components for Cortex M23 based System on Chip designs.

Corstone-300 combines various system IP components for Cortex M55 based System on Chip designs and the Ethos U55 accelerator for Artificial Intelligence and Machine Learning workloads.  Corstone-300 components support TrustZone with system-level Secure and a Non-secure operation.

Corstone-500 combines various system IP components for Cortex A5 Linux capable System on Chip designs using the AMBA protocol NIC-400 for up to 128 masters and 64 slaves, SoC-400 components for debug and trace and other Arm IP.

Arm System IP provides support for a variety of peripheral controllers which are usually managed in a sub-system based around the Advanced Microcontroller Bus Architecture (AMBA) Advanced Peripheral Bus (APB) which has reduced complexity interfaces, lower frequency operation and data width (32 bi

PL011 UART is an Advanced Microcontroller Bus Architecture (AMBA) slave module that connects to the Advanced Peripheral Bus (APB) used for serial communications.

PL022 SPI Synchronous Serial Port is an Advanced Microcontroller Bus Architecture (AMBA) slave module that connects to the Advanced Peripheral Bus (APB) used for synchronous serial communication with slave or master peripherals.

PL031 RTC is an Advanced Microcontroller Bus Architecture (AMBA) slave module that connects to the Advanced Peripheral Bus (APB) used provide a basic alarm function or long time base counter. A 32-bit free-running counter is incremented on successive rising edges of the 1Hz clock signal input. Th

DMA-230 is a low gate count (3-10k gates) DMA controller that is compatible with the Advanced Microcontroller Bus Architecture (AMBA) AHB-Lite protocol using a single AHB-Lite master for transferring data using 32-bit address and data buses. It perform memory-to-memory, memory-to-peripheral and p

The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral that is developed, tested, and licensed by ARM.

The DMA 350 is a high performance, high gate count DMA controller.

No matter how much work is done to ensure a design is correct it is likely issues will need to be discovered, identified and corrected. Ensuring an effective and efficient debug environment is important.

SoC-600 supports the Arm Debug Interface (ADI) v6 Architecture to build debug and trace into a SoC design. It can route debug and trace data over system master interfaces removing the need for a dedicated debug interface.

CoreSight SoC-400 is a debug subsystem design with Arm IP blocks for debug and trace in support of multi-processor SoCs. It contains components to implement CoreSight functionality for debug, trace, cross-triggering and timestamps. 

The Arm CoreSight Secure Debug Channel provides protection against debug access attacks allowing a debug certificate to be exchanged through a dedicated communication path for authenticating debug accesses.

The Arm CoreSight System Trace Macrocell (STM) - 500 is a trace source that provides trace data which conforms to the MIPI System Trace Protocol version 2 and provides timing-accurate trace data that is especially suitable for real-time applications. 

The Arm CoreSight System Trace Macrocell (STM) is a trace source that supports multiple processor cores and other components such as Direct Memory Access (DMA) controllers to pass trace data into the debug system. 

The Trace Memory Controller (TMC) enables trace data to be passed to system memory and other high speed devices and links in the System-on-Chip as part of the debug system. Debug system designs include the following components:

Tools and Models to support the SoC design and fabrication process provided by Arm as part of the AAA programme and by the SoC Labs community.

COIL-3D is a CAD tool for determining best performing inductor geometries for use in Inductive Coupling Link (ICL) based Three Dimensional Integrated Circuits (3D-ICs), developed at the University of Southampton, in collaboration with Arm Research.

Socrates assists in the design of a SoC interconnect by configuring the various Arm IP components (from the Arm IP catalog) to help the designer create an optimized and viable CoreLink Interconnect. 

Arm Development Studio is a professional software development solution for bare-metal embedded systems and Linux-based systems. It covers all stages in development from boot code and kernel porting to application and bare-metal debugging, including performance analysis.

Arm Fast Models provide a programming view simulation of Arm IP with profiling, debug and trace that allow software and hardware to be designed without the need for hardware, they support not just processors (Instruction Set Simulation) but memory and peripherals for complete system simulation.

Microcontroller Development Kit (MDK) for Armv8-M Architecture provides an integrated development environment (IDE) for developing embedded applications aimed at Arm Cortex-M processors including C/C++ compilers, various middleware components, as well as support for various debug adapters to conn

A full-system SystemC-based simulator for intermittent computing and energy-driven SoCs accurately modelling the interplay between energy-availability, power consumption, and execution in a closed feedback loop.