The MMU-500 System Memory Management Unit provides address and memory attribute translation from Virtual Memory spaces to the Physical Memory within the System on Chip. An SMMU is placed between a device and the system interconnect to translate addresses for Direct Memory Access requests for the device before the requests are passed into the system interconnect.

An SMMU might translate traffic from just one device or a set of devices, each device identified by a StreamID. The MMU-500 uses input from the requesting master to identify a context, the resources to use, including the translation tables, for the translation.

The MMU-500 implements a distributed Translation Buffer Unit (TBU) micro-architecture with direct point-to-point connections between each TBU and the centralized Translation Control Unit (TCU) for Page Table Walks (PTWs). Each TBU can be located in its own clock and power domain making it easy to co-locate the TBU with the device requiring translation.

It supports the translation formats of Armv7 and Armv8 architectures and performs Stage 1, Stage 2, or Stage 1 followed by Stage 2 translations for up to 128 active device contexts.