The Cortex-M4 implements the ARMv7-M architecture adding IEEE 754 compliant single precision Floating Point Unit and a range of saturating and SIMD instructions for Digital Signal Processing (DSP).

Supports Thumb-1 and Thumb-2 instructions with a 3-stage in-order pipeline, with hardware Divide and Multiply, privileged and nonprivileged mode (User Thread).

It supports Bit-banding regions in the lowest 1MB of the SRAM and Peripheral memory allowing individual bits to be toggled without performing a read-modify-write.

The Nested Vector Interrupt Controller (NVIC) supports up to 240 interrupt inputs from peripherals with programmable priority levels from 8 to 256 levels. 

The bus mechanism implements the 3x AHB-lite protocol interfaces (ICode, DCode, and System bus interfaces.) 

Optional Instruction (Embedded Trace Macrocell), Data Trace (DWT), and Instrumentation Trace (ITM), JTAG and Serial Wire Debug ports. Up to 8 breakpoints and 4 watchpoints.

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Diagram of M4 processor
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