Diagram of A32 processor
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The Cortex-A32 processor has an 8-stage, in-order pipeline implementing the 32-bit Armv8-A architecture with one to four cores with automatic data cache coherency, a shared Level 2 cache, 128 bit ACE, CHI or AXI system bus interface improving efficiency over Cortex A7 and A5.

Cortex-A32 can be configured as a uniprocessor without coherency logic or with Advanced Coherency Extensions (ACE) bus for fully coherent multiprocessing systems. The A32 Armv8-A has hardware virtualization support.


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