CoreLink CCI-500

Block diagram of CoreLink CCI-500
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CCI-500 Cache Coherent Interconnect provides high bandwidth access between CPUs and other SoC blocks including shared main memory and enables use of Arm big.LITTLE processing techniques between multiple cores. It supports up to four ACE masters, Arm processors, six ACE-Lite masters, eg. Mali GPU and six AXI4 slaves for memory, system peripherals, etc.

It implements a snoop filter within the interconnect that maintains a directory of all cache contents which avoids broadcasting coherency messaging to all agents improving latency and power consumption over the CCI-400. 

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