FPGA prototyping a System-on-a-Chip design enables the hardware design to be tested at or near real-time and software development to be started while the SoC implementation, verification, fabrication and packaging proceed in parallel.
The example design flow developed and described here targets the Xilinx ZCU104 development board, which has a large and capable ZYNQ UltraSCALE+ FPGA, and is fully supported out-of-the-box with Xilinx PYNQ development environment support.
The PYNQ platform is recommended in this case as this supports scripted control using Python to manage the FPGA overlays, and all through a built-in web-hosted server implemented on the ZYNQ Arm embedded processors that implements a Jupyter Notebook framework to support documentation and example usage.
Configuring the PYNQ platform
Comprehensive instructions for setting up the board are provided on the PYNQ site:
Follow the instructions for setting up the hostname, non-default password, and network parameters, and ensure the (re-booted) system offers network services.
FPGA structuring for SoC test-bench
The approach adopted is to use the ZYNQ processing system configuration to provide clocking and reset control to the SoC "Design under Test" (DUT).
The System-on-Chip design is instantiated at the chip level just inside the pad-ring - to present input/output/tri-state-control unidirectional signals rather than bidirectional/tri-stated I/O-s. Care is taken to ensure that the DUT is built independent of Xilinx system IP so in this example flow, the microcontroller design (https://soclabs.org/project/arm-cortex-m0-microcontroller in this case) is imported in the form of an external IP component.
The testbench "wraps" the DUT with a "socket" that is built, customized to the SoC design using the standard Xilinx Vivado "Block Design" IPXact design capture and tools, to include any specific peripherals - a UART communications channel in this case, plus generic General Purpose Input Output (GPIO) control ports to monitor or stimulate the IO ports.
The Arm-based ZYNQ processing subsystem is completely independent of the SoC DUT but provides the master clock for the device, which can be reconfigured in the Vivado editor. [Set to 20MHz for basic functional testing in the example implementation flow]
FPGA build scripts
Example scripts are provided in the soclabs-cortexm0-mcu gitlab directory:
The worked example was developed and tested with Xilinx(R) Vivado(R) tools version 2021.1, and may require minor updates for later versions of the toolchain.
The scripts should be run from the fpga implementation directory:
This uses tcl scripts to build the Cortex M) MCU is an "IP" component (using exactly the same RTL build deliverables up to the inside of the pad-ring of the SoC simulation and implementation flows) and then instantiate this in a ZCU104 test-bench wrapper - which uses the standard Vivado Block Design GUI flow.
Target board specific pin map and timing constraints are accessed from the target_fpga_zcu104 directory
The overlay and notebook output files are copied out to the directory:
These files are then ready for use as Xilinx PYNQ programmable logic overlays.
The PYNQ board, when successfully configured and connected to the network can be mounted as a file system and logged into from a browser.
The build scripts generate both the configuration bit-file (.bit) and hardware description (.hwh) files in the directory:
(default names of design_1.bit and design_1.hwh)
Simply copy the pynq/overlays/soclabs sub-tree in the PYNQ board pynq/overlays/ directory
These can be loaded interactively using an associated Jupyter Notebook.
Jupyter Notebook interaction
An example Jupyter Notebook and python device driver are provided in the directory:
(notebook named soclabs_cm0sdk_mcu.ipynb)
Simply copy the pynq/jupyter_notebooks/soclabs sub-tree in the PYNQ board pynq/jupyter_notebooks/ directory, which also includes a driver subdirectory.
Once correctly transferred over, it should be possible to connect and log into the PYNQ server from a web browser, and select the soclabs folder:
Select the ipynb notebook document and this will allow the overlay files to be loaded, checked and run to communicate with the MCU in the FPGA design (through a serial communications driver in this case):