Corstone 500 for A5

Corestone 500 block diagram
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Corstone-500 combines various system IP components for Cortex A5 Linux capable System on Chip designs using the AMBA protocol NIC-400 for up to 128 masters and 64 slaves, SoC-400 components for debug and trace and other Arm IP.

On-chip secondary cache can be added with the L2C-310 Level 2 Cache Controller.

For early software prototyping there is a Fixed Virtual Platform (FVP) Fast Model simulator and a ready prepared FPGA image.

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