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Block Diagram of SRAM chiplet

SRAM Chiplet

On-chip SRAM in ASICs can use a significant area, which equates to a significant cost. One solution is to make the memory off-chip. This project explores the use of Arm IP to create an SRAM chiplet design. The benefit  is that standard memory chiplets can be fabricated at lower cost and used across multiple projects, miminising silicon area to the unique project needs.

Reference Design
Active Project
Nanosoc ADC Integration
SoClabs

ADC Integration in nanoSoC
Rationale

The aim of this project is to define a mixed signal subsystem for the nanosoc reference design. 

In order to interface with real-world signals in a digital SoC, an analog to digital conversion is needed. The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system. 

Reference Design
Active Project
High bandwidth expansion subsystem block diagram
SoClabs

High Bandwidth Expansion Subsystem
The high bandwidth expansion subsystem is for use in systems where high bandwidth transfer to the hardware accelerator is required. This subsystem can be added to a larger SoC through the 2x full AXI ports (1 subordinate and 1 manager).
Reference Design
Active Project
Testboard and nanosoc Chip
SoClabs

nanoSoC Test/development Board

A physical test environment is required for ASIC devices fabricated following tape out. The nanoSoC test board provides a complete test environment for ASIC designs based on the nanoSoC reference design and enables the showcase of any custom designs that utilise it.  Reviewing the function of nanoSoC identifies a number of design criteria for the test board:

Reference Design
Active Project

DMA 350 integration with nanoSoC

The integration of the DMA350 into the nanosoc re-usable SoC architecture will improve the transfer bandwidth on DMA channels within the SoC.  This project integrates the DMA 350 into nanosoc, validates the integration and functionality of the DMA 350, and compares the performance of the DMA 350 to the PL230, that was the initial DMA controller integrated into nanosoc.

Reference Design
Active Project
dwn @ soclabs

nanosoc re-usable MCU platform
A small SoC development framework to support research demonstrator designs