Does the Fashion-MNIST dataset provide any natural advantages for processing. For example does the background being black mean the value 0 represents the background? 

Thanks for the project outline. Hopefully you are well into the Design of a 5x5 systolic array with input alignment. From that and looking at the data requirements you may be able to see how David Mapstone uses the DMA in the NanoSoC reference design to push/pull data from the accelerator. Your wrapper interface is going to differ from his implementation but hopefully it will act as a starting point. If you need any help then please let us know.

We also hope the item on how to structure a Project and our example projects help you get set up quickly for this project.

Hi,

How are you getting on developing the verification flow. Do you have a direction we are headed in? 

John.

Hi,

How are you getting on with the Project structure? More than happy to get any feedback on it. 

John.

Thanks for joining the contest and this looks like an exciting project. We look forward to seeing it develop. 

Meredith,

How is your project progressing? Did you ever find the issue re-occurred? Looking forward to hearing from you.

John.

The CoreLink NIC-450 you have identified provides some Arm blocks such as QoS-400 and QVN-400 that support Quality of Service protocols for specific latency concerns and other capabilities to better manage different data flows.

You have identified data movement efficiency and latency as key issues to overall performance of your deep learning tasks. You also mention using the CPU to fragment the image. Do you see the Quality of Service as important to your design?

Hopefully we have a clear pathway now to establish the Project and set up the repositories. If I understand things this Project will use the the NanoSoC reference design to push/pull data from the accelerator. 

Thanks for the great description of the project. I quick look suggests integration of NanoSoC MO and DMA controllers with your project. I hope I have not mis-represented this. Look forward to seeing the Project structure to bring in the various parts and the design flow environment for the project.

We have had a good response to the contest, especially on 1) H/W implementation track. 

The original deadline of the 5 June was chosen so we could review projects at the start of July and let people know if they were going to get an invite for IEEE SOCC 2023 in September 2023 in Santa Clara, CA, USA where the final contest judgements will be made. Our aim was to allow people who need to make travel and entry visa arrangements time to plan. We still intend to review in July and offer direct invites but people are also free to enter the contest and make their own plans to attend IEEE SOCC 2023 and join us all there.

We look forward to getting a few more entries especially on 2) Collaboration/Education track and of course to seeing people at IEEE SOCC 2023.