System Trace Macrocell
The Arm CoreSight System Trace Macrocell (STM) is a trace source that supports multiple processor cores and other components such as Direct Memory Access (DMA) controllers to pass trace data into the debug system.
It is a successor to the Instrumentation Trace Macrocell (ITM) using an AXI slave interface to provide higher throughput of trace data from SoC components. It also implements a hardware event interface to generate trace when signals are asserted on it.
It supports use of the CoreSight authentication signals to control debug permissions.
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When is the default debug componentry enough?
This is one of the basic questions for a SoC design. Perhaps a nice worked example of a simple extension to the default configured debug environment for some exemplar targets. With technical manuals they always define the interfaces well but leave the 'fluffy cloud' for where the custom SoC design happens. Adding a worked example of some design in this fluffy cloud would be a useful piece of content to add to SoC Labs and others might also like to add some comment below to share their knowledge.