The Arm CoreSight System Trace Macrocell (STM) - 500 is a trace source that provides trace data which conforms to the MIPI System Trace Protocol version 2 and provides timing-accurate trace data that is especially suitable for real-time applications. 

The STM-500 can receive instrumentation data from multiple processors and processes via the AXI slave interface or  generate trace when signals are asserted on the hardware event interface.  The Arbiter selects the input data with higher priority assigned to AXI transactions passing to the packet generation logic, which timestamps and organizes the trace data according to the STPv2 protocol. The depth of the FIFO buffers can be configured to match the necessary system demand, deeper buffers improve performance by trading area and power consumption. Supports both 64-bit and 32-bit systems.

For interaction with DMA controllers, the STM provides a DMA request interface that is compatible with the AMBA DMA Controller DMA-330.

It supports CoreSight authentication signals to control debug permissions.