Diagram of M0+ processor
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The Cortex-M0+ implements the ARMv6-M architecture with a two-stage in-order pipeline and additonal clock gating to improve efficiency and a Memory Protection Unit supporting 8 protection regions to separate processes and privileges in the same gate count as MO.

Supports Thumb (16 bit) and subset of Thumb-2 (32/16 bit) instructions. The Memory Protection Unit supports the ARMv6 Protected Memory System Architecture model.

The bus mechanism (Advanced Microcontroller Bus Architecture AMBA-3) implements the AHB-lite protocol which is a simplified version of Advanced High-performance Bus (AHB) using a single master design. 

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