A large part of the behavioural design phase of a project is actually the verification of the design at multiple levels of abstraction. This ideally involves a significant amount of verification at the accelerator internal component level (unit testing), the accelerator engine as a whole, the accelerator at the wrapper level and then system tests.
Once an accelerator has been designed and unit tested, it is then a crucial step to integrate it into a system and then verify that it has been connected correctly and is able to communicate with other devices within the system. In a system such as NanoSoC, which has multiple initiators such as a Microprocessor, DMA Controller and Debug port, it is important that these are actually able to communicate over AHB (and other interfaces if implemented) to the accelerator.
As an example, the hashing unit submodule of the SHA-2 Hashing accelerator has been taken and integrated into a NanoSoC instance. From here, the next step is to use the system initiators to perform some limited verification on the accelerator to prove they are connected together.
The premise of the verification is to perform simple reads and writes from the Debug Port directly to the accelerator via the AHB-Lite Bus Matrix. By writing known stimulus data to a particular address within the accelerators address-space, the accelerator will be able to process this data and then generate data at its output which can then be read by over the debug port and then externally (by a script or by the testbench) verified against reference data (generated by an Algorithmic model of the accelerator) after the fact. This reduces the complexity overhead with designing, writing, compiling and loading code to run on the CPU or DMA Controller for initial verification.
The accelerator is comprised of an AHB Interface, two packet translators – one to produce 512 bit packets to feed into the engine and one to deconstruct 256 bit packets into 32 bit AHB packets – some input/output buffers, the engine and a hard-coded configuration module to simplify implementation at this stage.
The diagram below shows a simplified structure of our NanoSoC with AHB initiators at the top and Targets at the bottom:
The accelerators address map will be visible to all initiators in the system in the expansion region on the global address map.
Accelerator Address Space
The accelerator will have 4KiB of address space in the first expansion region of the address map.
The first stage of verification is to make sure the accelerator is connected as specified and that it is assessable in the address map.
A simple verification could use a python model of the accelerator to generate 32-bit data words which can be fed into the accelerator wrapper. There are many different approaches to get the data to the accelerator but the simplest is to perform the verification outside of the system and to directly feed data into the system over the debug interface. As we are not concerned with performance at this point, we are not worried about the timing overhead compared to pre-loading the system with test stimulus.
The ADP interface can be used to write the data words to the Accelerator Input region of the address-map and then poll the output data port for a calculated response. As there are currently no registers or interfaces for the accelerator to tell the system that it has valid data, a short delay may be required between writing to and reading from the accelerator ports.
Once the data has been read from the accelerator, a simple script or part of the testbench is able to compare the read data with the expected reference data generated from the python model of the accelerator. This will be able to tell whether the verification passed or failed.
- What needed to be done to generate the stimulus?
- How was the stimulus fed into the Testbench?
- How was data verification actually performed?
- What should people take away from this?
- Where is most time spend?
- What is it worth having a good understanding of?
- What do these results of this verification actually mean?
- What are the next steps in System Verification?