L2C-310 Level 2 Cache Controller

Block diagram for CoreLink L2C-310 Level 2 Cache Controller
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The Level 2 Cache Controller L2C-310 improves memory access speed within a SoC by implementing Level 2 memory caching (access within 8 cycles) using slave and master AMBA AXI interfaces, between Level 1 instruction and data caches (1-2 cycles) and  Level 3 main memory (30-100 cycles). The cache available can be configured from 16KB to 8MB. It supports the TrustZone architecture for enhanced security. 

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