A Generic Interrupt Controller  providing registers for managing interrupt sources, interrupt behavior, and interrupt routing for up to 128 Armv8.0 A class processor cores such as the A53. It implements version 3.0 of the ARM Generic Interrupt Controller Architecture Specification. 

The GIC-500 has a 64-bit AMBA AXI4 master port to access main memory. The hypervisor or OS software is responsible for allocating memory to the GIC-500. A 32-bit AMBA AXI4 slave interface handles all message-based interrupts. The GIC-500 GIC Stream Protocol Interface uses a pair of 16-bit AMBA AXI4-Stream interfaces to send interrupts and receive notifications from a core. It also supports the generation of all cores (SPI) and core specific (PPI) interrupts through physical signals.